• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.2
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• pp.542-558
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• 2023

A digital focus index (DFI) is a value used to determine image focus in scientific apparatus and smart devices. Automatic focus (AF) is an iterative and time-consuming procedure; however, its processing time can be reduced using a general processing unit (GPU) and a multi-core processor (MCP). In this study, parallel architectures of a minimax search algorithm (MSA) are applied to two DFIs: range algorithm (RA) and image contrast (CT). The DFIs are based on a histogram; however, the parallel computation of the histogram is conventionally inefficient because of the bank conflict in shared memory. The parallel architectures of RA and CT are constructed using parallel reduction for MSA, which is performed through parallel relative rating of the image pixel pairs and halved the rating in every step. The array size is then decreased to one, and the minimax is determined at the final reduction. Kernels for the architectures are constructed using open source software to make it relatively platform independent. The kernels are tested in a hexa-core PC and an embedded device using Lenna images of various sizes based on the resolutions of industrial cameras. The performance of the kernels for the DFIs was investigated in terms of processing speed and computational acceleration; the maximum acceleration was 32.6× in the best case and the MCP exhibited a higher performance.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.339-349
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• 2017

This paper proposes a four-stage algorithm for detecting lanes on a driving car. In the first stage, it extracts region of interests in an image. In the second stage, it employs a median filter to remove noise. In the third stage, a binary algorithm is used to classify two classes of backgrond and foreground of an input image. Finally, an image erosion algorithm is utilized to obtain clear lanes by removing noises and edges remained after the binary process. However, the proposed lane detection algorithm requires high computational time. To address this issue, this paper presents a parallel implementation of a real-time line detection algorithm on a multi-core architecture. In addition, we implement and simulate 8 different processing element (PE) architectures to select an optimal PE architecture for the target application. Experimental results indicate that 40×40 PE architecture show the best performance, energy efficiency and area efficiency.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• Journal of the Korea Society of Computer and Information
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• v.18 no.11
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• pp.1-12
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• 2013

In multi-core processors, Last Level Cache(LLC) can reduce the speed gap between the memory and the core. For this reason, LLC has big impact on the performance of processors. LLC is composed of shared cache and private cache. In computer architecture community, most researchers have mainly focused on the management techniques for shared cache, while management techniques for private cache have not been widely researched. In conventional private LLC, memory is statically assigned to each core, resulting in serious performance degradation when the workloads are not fairly distributed. To overcome this problem, this paper proposes the replacement policy for managing private cache of LLC efficiently. As proposed core-aware cache replacement policy can reconfigure LLC dynamically, hit rate of LLC is increases drastically. Moreover, proposed policy uses 2-bit saturating counters to improve the performance. According to our simulation results, the proposed method can improve hit rates by 9.23% and reduce the access time by 12.85% compared to the conventional method.

• Journal of Information Management
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• v.28 no.4
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• pp.16-33
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• 1997

Recently, the construction of Digital Library is one of the hottest issues among librarians. This Study focused on how small libraries can produce digital data and construct Web database. In particular, the production and application of digital data, using PDF file, were described in detail.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.700-702
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• 1998

자바(Java)의 수행 성능을 향상시키기 위한 방법으로 자바 프로세서가 제안되었다. 그러나 현재의 자바 프로세서는 자바 가상 머신(Java Virtual Macjine)의 구조만을 고려한 것이다. 본 논문에서는 기존 자바 프로세서의 성능을 향상시키는 자바 프로그래밍에서 사용되는 다중스레드를 직접 지원하는 새로운 자바 프로세서인 동시 다중스레드 자바 칩(Simultaneous Multithreaded Java Chip SMTJC)을 제안한다. SMTJC은 두 개의 독립적인 스레드를 동시에 수행함으로써, 자바 프로그램에서의 명령어 수준 병렬성(Instruction level parallelism)을 향상시킨다. 다중스레드 수행을 위해 새로운 스택 캐쉬의 구조 및 운영 방법을 사용한다. JavaSim을 통한 시뮬레이션은 SMTJC 이 기존 자바 프로세서에 비해 이중 스택 캐쉬와 추가적 처리 유닛들로 인해 1.28~2.00의 전체적 수행 성능이 향상됨을 보여준다. 본 연구는 하드웨어와 소프트웨어의 상호 보안적인 기술적 경향을 배경으로 자바의 언어적 특성을 고려한 프로세서를 설계, 지원함으로써 자바 프로세서의 성능 향상을 도모하고 있다.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.233-239
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• 2015

This paper describes a method that is integrated trace for real-time virtualization environment. This method has solved the problem that the performance trace may not be able to analyze integrated method between heterogeneous operating systems which is consists of real-time operating systems and general-purpose operating system. In order to solve this problem, we have attempted to reuse the performance analysis function in general-purpose operating system, thereby real-time operating systems can be analyzed along with general-operating system. Furthermore, we have implemented a prototype based on ARM Cortex-A15 dual-core processor. By using this integrated trace method, real-time system developers can be improved productivity and reliability of results on real-time virtualization environment.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.4
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• pp.235-243
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• 2008

In this paper, a software-based Digital Radio Modiale(DRM) receiver is implemented on a Digital Signal Processor(DSP). DRM stands for the European radio broadcasting standard to bring AM radio into digital radio, designed to work at frequencies below 30MHz. DRM can offer various data services such as text messaging and slideshow services as well as audio services. The DRM receiver implemented on the Tensilica DSP core performs well at low signal strength indication of -102dBm.

• Electronics and Telecommunications Trends
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• v.28 no.2
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• pp.1-10
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• 2013

1980년대와 1990년대가 서버와 데스크톱 중심 컴퓨팅의 시대였다고 한다면 2000년대 들어 모바일 분야를 포함하는 임베디드 프로세서 시장이 급격히 확장되며 임베디드 중심 시대로 산업구조가 재편되고 있다. 그리고, 2010년대에는 임베디드 프로세서 시장이 더욱 확대되고 기술도 더불어 발전되고 있는데, 최근 기술을 주도하고 있는 뜨거운 용어 중의 하나가 이기종 멀티코어 컴퓨팅이라 할 수 있다. 시장이 요구하는 고성능 컴퓨팅을 수용하고 임베디드 기기의 특성상 저전력을 실현해야 하는 현실적 문제를 해결하기 위한 이기종 멀티코어 하드웨어가 임베디드 기기에도 적용을 앞다투고 있는 상황이며, 적절한 응용 콘텐츠에 맞춰 이기종 멀티코어 하드웨어를 활용하기 위한 소프트웨어에 대한 관심과 발전도 발 맞춰 진행되고 있다. 이에 본고에서는 임베디드 기기 분야에 한정하여 이기종 멀티코어 하드웨어와 소프트웨어의 기술 동향을 살펴보고자 한다.

• Journal of the Korea Society of Computer and Information
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• v.9 no.1
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• pp.1-8
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• 2004

XML is becoming the standard of the new document exchanging. Due to the ablility expressing various types of document structure through XML, RosettaNet and BizTalk are using XML as a core technology in the part of e-Business. Framework is running Business process each other different standard. Internal documents in each company should be transformed differently without any loss to work with other companies. In this paper, transforming Processor based on XML mapping information from XML document information.