• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.497-508
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• 2008

Mobile Multimedia File System, MNFS, is a file system which extensively exploits NAND FLASH Memory, Since general Flash file systems does not precisely meet the criteria of mobile devices such as MP3 Player, PMP, Digital Camcorder, MNFS is designed to guarantee the optimal performance of FLASH Memory file system. Among many features MNFS provides, there are three distinguishable characteristics. MNFS guarantees, first, constant response time in sequential write requests of the file system, second, fast file system mounting time, and lastly least memory footprint. MNFS implements four schemes to provide such features, Hybrid mapping scheme to map file system metadata and user data, manipulation of user data allocation to fit allocation unit of file data into allocation unit of NAND FLASH Memory, iBAT (in core only Block Allocation Table) to minimize the metadata, and bottom-up representation of directory. Prototype implementation of MNFS was tested and measured its performance on ARM9 processor and 1Gbit NAND FLASH Memory environment. Its performance was compared with YAFFS, NAND FLASH File system, and FAT file system which use FTL. This enables to observe constant request time for sequential write request. It shows 30 times faster mounting time to YAFFS, and reduces 95% of HEAP memory consumption compared to YAFFS.

• The KIPS Transactions:PartD
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• v.8D no.4
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• pp.347-360
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• 2001

The most expensive spatial operation in spatial databases is a spatial join which computes a combined table of which tuple consists of two tuples of the two tables satisfying a spatial predicate. Although the execution time of sequential processing of a spatial join has been so far considerably improved, the response time is not tolerable because of not meeting the requirements of interactive users. It is usually appropriate to use parallel processing to improve the performance of spatial join processing. However, as the number of processors increases, the efficiency of each processor decreases rapidly because of the disk bottleneck and the overhead of message passing. This paper proposes the method of task allocation to soften the disk bottleneck caused by accessing the shared disk at the same time, and to minimize message passing among processors. In order to evaluate the performance of the proposed method in terms of the number of disk accesses and message passing, we conduct experiments on the two kinds of parallel spatial join algorithms. The experimental tests on the MIMD parallel machine with shared disks show that the proposed semi-dynamic task allocation method outperforms the static and dynamic task allocation methods.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.535-544
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• 2003

Integrated services networks should guarantee end-to-end delay bounds for real-time applications to provide high quality services. A real-time scheduler is installed on all the output ports to provide such guaranteed service. However, scheduling algorithms studied so far have problems with either network utilization or scalability. Here, network utilization indicates how many real-time sessions can be admitted. In this paper, we propose service curve allocation schemes that result in both high network utilization and scalability in a service curve algorithm. In service curve algorithm, an adopted service curve allocation scheme determines both network utilization and scalability. Contrary to the common belief, we have proved that only a part of a service curve is used to compute deadlines, not the entire curve. From this fact, we propose service curve allocation schemes that result in a constant time for computing deadlines. We through a simulation study that our proposed schemes can achieve better network utilizations than Generalized processor Sharing (GPS) algorithms including the multirate algorithm. To our knowledge, the service curve algorithm adopting our schemes can achieve the widest network utilization among existing scheduling algorithms that have the same scalability.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.266-271
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• 1999

The purpose in this study has to development the system on increasing operation of old-typed transceiver for solve the question that limited allocation frequencies and continuesly icreasment of traffic. Therefore, we are desigened the remote control system that has the function for variable channels, PTT and monitoring of transmission power and frequencies. Exchange of control data is to hold in common the twist two-wire or telephone line for the voice transmission. The H/W is consist of FSK and MCS-51 processor which are up-down control of channel, n control and monitoring display by serial data transmission. According to the simplex traffic operation is designed the algorithm of serial data transmission by sequential transmission sequence and protocol. The S/W of sequential transmission sequence is designed to usefully the intergrated communications system which is able to connection between the multi-transceiver and multi-terminal by master processor.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.418-429
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• 2001

Recently, a GIS has been applicable to the most important computer applications such as urban information systems and transportation information systems. These applications require spatial operations for an efficient management of a large volume of data. In particular, a spatial join among basic operations has the property that its response time is increased exponentially according to the number of spatial objects included in the operation. Therefore, it is not proper to the systems demanding the fast response time. To satisfy these requirements, the efficient parallel processing of spatial joins has been required. In this paper, the efficient method for creating and allocating tasks to balance statically the load of each processor in a parallel spatial join is presented. A task graph is developed in which a vertex weight is calculated by the cost model I have proposed. Then, it is partitioned through a graph partitioning algorithm. According to the experiments in CC16 parallel machine, our method made an improvement in the static load balance by decreasing the variance of a task execution time on each processor.

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.4
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• pp.18-29
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• 2019

A dynamic adaptive streaming server consumes high processor power because it handles a large amount of transcoding operations at a time. For this purpose, multi-processor architecture is mandatory for which effective transcoding task distribution strategies are essential. In this paper, we present the design and implementation details of the transcoding workload distribution schemes at a 2-tier (frontend node and backend node) transcoding server. For this, we implemented four schemes: 1) allocation of transcoding tasks to appropriate back-end nodes, 2) task scheduling in the back-end node and 3) the communication between front-end and back-end nodes. Experiments were conducted to compare the estimated and the actual power consumption in a real testbed to verify the efficacy of the system. It also proved that the system can reduce the load on each node to optimize the power and time used for transcoding.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.5
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• pp.1017-1026
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• 2012

Due to acceleration of the IT industry and the environment for a variety of media in modern society, such as real-time video images 3D-TV is a very important issue. These high-quality live video is being applied to various fields such as CCTV footage has become an important performance parameters. However, these high quality images, even vulnerable because of shortcomings secure channel or by using various security algorithms attempt to get rid of these disadvantages are underway very active. These shortcomings, this study added extra security technologies to reduce the processing speed image processing itself, but by adding security features to transmit real-time processing and security measures for improving the present.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.1-10
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• 2001

본 논문에서는 부쉬 트리를 할당 트리로 변환한 후 결합 연산을 수행하면서 실제 실행시간을 동적으로 계산하고 그 결과에 의해 실시간에 프로세서를 할당하는 동적 프로세서 할당 기법을 이용한 파이프라인 해쉬 결합 알고리즘을 제안하였다. 프로세서를 할당하는 과정에서 초기 릴레이션의 기본 정보만을 이용하여 미리 프로세서를 할당하는 기존의 정적 프로세서 할당 기법은 정확한 실행시간을 예측할 수 없었다. 따라서 본 논문에서는 할당 트리 각 노드의 실행결과를 포함한 결합 과정 중의 정보를 다음 노드의 실행시간에 충분히 반영하는 동적 프로세서 할당 기법을 제안하였으며, 이로써 프로세서를 효율적으로 분배하고 전체적인 실행시간을 최소화하였다. 또한 전체적인 질의 실행시간을 줄이기 위하여 결합 가능성이 없는 튜플들을 제거한 후 결합 연산을 수행할 수 있도록 해쉬 필터 기법을 이용하였다. 결합 연산을 수행하기에 앞서 모든 결합 속성 값에 대해 해쉬 필터를 생성하는 정적 필터 기법은 모든 결합 연산의 중간 결과로 발생할 수 있으나 최종 결과 릴레이션의 튜플이 될 수 없는 튜플들까지도 모두 추출이 가능하다. 따라서 각각의 결합 연산 직전에 해쉬 필터를 생성하는 동적 필터 기법에 비해 결합 가능성이 없는 튜플을 최대한 제거할 수 있으며 이로써 결합 연산의 실행비용을 크게 줄일 수 있었다.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.3
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• pp.144-154
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• 2001

다중 결합 질의에 포함된 다수의 결합 연산지를 효율적으로 처리하기 위해 서는 효율적인 병렬 알고리즘이 필요하다. 최근 다중 해쉬 결합 질의의 처리를 위해 할당 트리를 이용한 방법이 가장 우수한 것으로 알려져 있다. 그러나 이 방법은 실제 결합 시에 할당 트리의 각 노드에서 필연적인 지연이 발생되는 데 이는 튜플-시험 단계에서 외부 릴레이션을 디스크로부터 페이지 단위로 읽는 비용과 이미 읽는 페이지에 대한 해쉬 결합 비용간의 차이에 의해 발생하게 된다. 이들 사이의 실행시간을 가급적 일치시키기 위한 '페이지 실행시간 동기화'기법이 제안되었고 이를 통해 할당 트리 한 노드 실행에 있어서의 지연 시간을 줄일 수 있었다. 하지만 지연 시간을 최소화하기 위해 할당되어질 프로세서의 수 즉, 페이지 실행시간 동기화 계수(k)는 실제 결합 시의 결합률에 따라 상당한 차이를 보이게 되고 결국, 이 차이를 고려하지 않은 다중 해쉬 결합은 성능 면에서 크게 저하될 수밖에 없다. 본 논문에서는 결합 이전에 어느 정도의 결합률을 예측할 수 있다는 전제하에 다중 해쉬 결합 실행 시에 발생할 수 있는 지연 시간을 최소화 할 수 있도록 결합률에 따라 최적의 프로세서들을 노드에 할당함으로서 다중 해쉬 결합의 실행 성능을 개선하였다. 그리고 분석적 비용 모형을 세워 기존 방식과의 다양한 성능 분석을 통해 비용 모형의 타당성을 입증하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.196-198
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• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach