• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.194-196
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• 2005

The command processor in satellite handles the capability of the process of command transmitted from ground station and deliver the processed data to on board computer in satellite. The command processor is consisted of redundant box to increase the reliability and availability of the capability. At each command processor, the processing time of each command processor is different, so the mismatch of processing time makes it difficult to timely synchronize the reception to on board computer and even will be became worse under the command processor's fault. To minimize the tine loss induced by the command processor's fault on board computer must analyze the time distribution of command propagation. This paper presents the logic of minimizing the delay error of command propagation the logic of analyzing the output of command processor.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.1
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• pp.9-16
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• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• Journal of IKEEE
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• v.18 no.3
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• pp.392-397
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• 2014

In this paper, we propose a memory operation system architecture for memory latency penalty reduction in SIMT architecture based stream processor. The proposed architecture applied non-blocking cache architecture to reduce cache miss penalty generated by blocking cache architecture. We verified that the proposed memory operation architecture improve the performance of the stream processor by comparing processing performances of various algorithms. We measured the performance improvement rate that was improved in accordance with the ratio of memory instruction in each algorithm. As a result, we confirmed that the performance of stream processor improves up to minimum 8.2% and maximum 46.5%.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Transactions of the Korean Society of Automotive Engineers
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• v.8 no.3
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• pp.190-197
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• 2000

A graphic vehicle modeling pre-processing program and a visualization post-processing program have been developed for AutoDyn7, which is a special program for vehicle dynamics. The Rapid-App for GUI(Graphic User Interface) builder and the Open Inventor for 3D graphic library have been employed to develop these programs in Silicon Graphics workstation. A Graphic User Interface program integrates vehicle modeling pre-processor, AutoDyn7 analysis processor, and visualization post-processor. In vehicle modeling pre-processor, vehicle hard point data for a suspension model are automatically converted into multibody vehicle system data. An interactive graphics capabilities provides suspension modeling aides to verify user input data interactively. In visualization post-processor, vehicle virtual test simulation results are animated with virtual testing environments.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• ETRI Journal
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• v.31 no.6
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• pp.709-716
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• 2009

In this paper, we propose a novel reconfigurable processor using dynamically partitioned single-instruction multiple-data (DP-SIMD) which is able to process multimedia data. The SIMD processor and parallel SIMD (P-SIMD) processor, which is composed of a number of SIMD processors, are usually used these days. But these processors are inefficient because all processing units (PUs) should process the same operations all the time. Moreover, the PUs can process different operations only when every SIMD group operation is predefined. We propose a processor control method which can partition parallel processors into multiple SIMD-based processors dynamically to enhance efficiency. For performance evaluation of the proposed method, we carried out the inverse transform, inverse quantization, and motion compensation operations of H.264 using processors based on SIMD, P-SIMD, and DP-SIMD. Experimental results show that the DP-SIMD control method is more efficient than SIMD and P-SIMD control methods by about 15% and 14%, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.24-29
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• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.