• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.301-304
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• 2000

In this paper, we designed a 256-point FFT processor using VHDL. We adopted Radix-2$^2$SDC(Single-path Delay Commutator) architectures to reduce the number of complex multipliers. We confirmed the operation of the design through simulation using Altera MAX+PLUS II.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.381-382
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• 2008

• 전산구조공학
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• 제9권3호
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• pp.69-74
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• 1996

본 고에서는 1. PENTAGON 프로그램 소개 - 1) 개발배경 2) 프로그램의 구성 2. PENTAGON의 module별 기능 - 1) Pre-processor module 2) Processor module (FRONTDBX) 3) post-processor module (PENPOST) 등에 대하여 알아보았다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.837-840
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• 2005

This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1177-1180
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• 2005

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• ETRI Journal
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• 제37권1호
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• pp.107-117
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• 2015

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2006년도 추계 종합학술대회 논문집
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• pp.642-646
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• 2006

본 연구는 생산 공정의 입출고관리시스템에 관한 연구이다. 기존의 자재 관리 시스템은 바코드를 이용하는 경우가 많지만 대부분의 업체는 많은 불편함을 호소하고 있다. RFID 기술을 입출고관리시스템에 적용하면 자재의 정보를 효율적으로 관리할 수 있고 수작업의 감소로 인해 시간과 비용을 절약할 수 있다. 본 연구는 생산 공정의 입출고관리시스템을 위해 입고 프로세서, 출고 프로세서, 제고 프로세서, 자재소요량프로세서를 설계하였다. 이러한 프로세서를 검증할 수 있도록 사용자 입장에서 평가하여 검증한다.

• 한국도서관정보학회지
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• 제12권
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• pp.199-232
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• 1985

Word processor having the functions of a typewriter and a computer together have been used as a powerful tools for office automation. The purpose of this study is to find out the possible areas of the word processing a n.0, pplication in the library operations. For the study, the general concept, developmental process, structure, functions, kinds and suggested a n.0, pplicable areas in the library operations of word processor were investigated. Then, the cases of real a n.0, pplications of word processor in the library field were examplified. In conclusion, the areas where word processor can be of benefit to library workers can be summarized as follows, 1) Orders of books and periodical acquisitions, 2) On-line searching, and storage and editing of input as required, 3) Production of catalogues, and abstracting and indexing bulletin, 4) Budget control, circulation control, and serial control.

• 전자공학회논문지B
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• 제31B권1호
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• pp.49-56
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• 1994

This paper describes the design principles and methods of electronic processor for thermal imager with the SPRITE detector, operating in the 8-12 micron band. The thermal imager consists of a optical scanner containing the detector and an electrical signal processor. The optical scanner utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using 5 elements of the detector. And the electronic processor has pre-processing of 5 chnanel's thermal signal from the detector, and performs digital scan conversion to reform the parallel data stream into serial analog data compatible with conventional RS-170 video. Through the designed electronic processor, we have acquired a satisfactory thermal image. And the MRTD (Minimum Resolvable Temperature Difference) is 0.5$^{\circ}$K at 7.5 cycles/mm.