• The KIPS Transactions:PartD
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• v.17D no.5
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• pp.353-358
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• 2010

Unlike the traditional databases, queries on XML streams are restricted to a real time processing and memory usage. In this paper, a robust labeling scheme is proposed, which quickly identifies structural relationship between XML fragments. The proposed labeling scheme provides an effective query processing by removing many redundant operations and minimizing the number of fragments being processed. In experimental results, the proposed labeling scheme efficiently processes query processing and optimizes memory usage.

• Phonetics and Speech Sciences
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• v.9 no.3
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• pp.57-65
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• 2017

The current study explored how Korean-speaking children processed the multiple acoustic cues (VOT and f0) for the stop laryngeal contrast (/t'/, /t/, and /$t^h$/) and examined whether individual perceptual strategies could be related to a general cognitive ability performing executive functions (EF). 15 children (aged from 7 to 8) participated in the speech perception task identifying the three Korean laryngeal stops (3AFC) on listening to the auditory stimuli of C-/a/ with synthetically varying VOT and f0. They completed a series of EF tasks to measure working memory, inhibition, and cognitive shifting ability. The findings showed that children used the two cues in a highly correlated manner. While children utilized VOT consistently for the three laryngeal categories, their use of f0 was either reduced or enhanced depending on the phonetic categories. Importantly, the children's processing strategies of a f0 suppression for a tense-aspirated contrast were meaningfully associated with children's better cognitive abilities such as working memory, inhibition, and attentional shifting. As a preliminary experimental investigation, the current research demonstrated that listeners with inefficient processing strategies were poor at the EF skills, suggesting that cognitive skills might be responsible for developmental variations of processing sub-phonemic information for the linguistic contrast.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.8-11
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• 2020

4 차 산업혁명 시대의 도래와 함께 AI, ICT 기술의 융합이 진행됨에 따라, 유저 레벨의 디바이스에서도 AI 서비스의 요청이 실현되었다. 이미지 처리와 관련된 AI 서비스는 피사체 판별, 불량품 검사, 자율주행 등에 이용되고 있으며, 특히 Deep Convolutional Neural Network (DCNN)은 이미지의 특색을 파악하는 데 뛰어난 성능을 보여준다. 하지만, 이미지의 크기가 커지고, 신경망이 깊어짐에 따라 연산 처리에 있어 낮은 데이터 지역성과 빈번한 메모리 참조를 야기했다. 이에 따라, 기존의 계층적 시스템 구조는 DCNN 을 scalable 하고 빠르게 처리하는 데 한계를 보인다. 본 연구에서는 DCNN 의 scalable 하고 빠른 처리를 위해 3 차원 메모리 구조의 Processing-In-Memory (PIM) 가속기를 제안한다. 이를 위해 기존 3 차원 메모리인 Hybrid Memory Cube (HMC)에 하드웨어 및 소프트웨어 모듈을 추가로 구성하였다. 구체적으로, Processing Element (PE)간 데이터를 공유할 수 있는 공유 캐시 및 소프트웨어 스택, 파이프라인화된 곱셈기 및 듀얼 프리페치 버퍼를 구성하였다. 이를 유명 DCNN 알고리즘 LeNet, AlexNet, ZFNet, VGGNet, GoogleNet, RestNet 에 대해 성능 평가를 진행한 결과 기존 HMC 대비 40.3%의 속도 향상을 29.4%의 대역폭 향상을 보였다.

• Journal of Information Processing Systems
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• v.11 no.1
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• pp.39-56
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• 2015

Continuous multi-interval prediction (CMIP) is used to continuously predict the trend of a data stream based on various intervals simultaneously. The continuous integrated hierarchical temporal memory (CIHTM) network performs well in CMIP. However, it is not suitable for CMIP in real-time mode, especially when the number of prediction intervals is increased. In this paper, we propose a real-time integrated hierarchical temporal memory (RIHTM) network by introducing a new type of node, which is called a Zeta1FirstSpecializedQueueNode (ZFSQNode), for the real-time continuous multi-interval prediction (RCMIP) of data streams. The ZFSQNode is constructed by using a specialized circular queue (sQUEUE) together with the modules of original hierarchical temporal memory (HTM) nodes. By using a simple structure and the easy operation characteristics of the sQUEUE, entire prediction operations are integrated in the ZFSQNode. In particular, we employed only one ZFSQNode in each level of the RIHTM network during the prediction stage to generate different intervals of prediction results. The RIHTM network efficiently reduces the response time. Our performance evaluation showed that the RIHTM was satisfied to continuously predict the trend of data streams with multi-intervals in the real-time mode.

• Journal of the Korea Society of Computer and Information
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• v.17 no.7
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• pp.1-11
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• 2012

As process technology scales down, the number of cores integrated into a processor increases dramatically, leading to significant performance improvement. Especially, the GPU(Graphics Processing Unit) containing many cores can provide high computational performance by maximizing the parallelism. In the GPU architecture, the access latency to the main memory becomes one of the major reasons restricting the performance improvement. In this work, we analyze the performance improvement of the 3D GPU architecture compared to the 2D GPU architecture quantitatively and investigate the potential problems of the 3D GPU architecture. In general, memory instructions account for 30% of total instructions, and global/local memory instructions constitutes 60% of total memory instructions. Therefore, the performance of the 3D GPU is expected to be improved significantly compared to the 2D GPU by reducing the delay of memory instructions. However, according to our experimental results, the 3D architecture improves the GPU performance only by 2% compared to the 2D architecture due to the memory bottleneck, since the performance reduction due to memory bottleneck in the 3D GPU architecture increases by 245% compared to the 2D architecture. This paper provides the guideline for suitable memory design by analyzing the efficiency of the memory architecture in 3D GPU architecture.

• Journal of Digital Convergence
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• v.19 no.1
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• pp.355-360
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• 2021

In this study, the factors of confirmation bias that may occur in the initial user experience stage were analyzed using a honeycomb model by deriving user experience factors for each factor. In the initial user experience stage, confirmation bias occurs in the impression stage. At the processing stage of memory, sensory memory, working memory, and long-term memory, which stores and retrieves selective memory, were closely related. Confirmation bias was classified into visibility, correlation, memory, clarity, and universality in the usability part, and satisfaction, joy, and dissatisfaction were derived as emotional factors. As a result of the analysis with the honeycomb model, visuality, clarity, universality in the usability factor, and joy in the emotional factor had little effect on the confirmation bias, and satisfaction and dissatisfaction were analyzed as the main factors of the confirmation bias in the correlation, memory and emotional factors. This study is meaningful in that it can be usefully used as a reference material for companies that customize design patterns for the factor of confirmation bias.

• Korean Journal of Cognitive Science
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• v.11 no.3_4
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• pp.13-22
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• 2000

The present study examined the role of spatial attention in implicit memory for words when the word identity processing was not required. Spatial attention to the identity-irrelevant perceptual features of the words was manipulated by using a visual search task (Experiment 1) or a focused attention task (Experiment 2). In two e experiments. a significant priming effect was not found for the target words as well as for the distractor words. Implicit memory for words was not affected by spatial attention on the perceptual properties of the words. indicating that the word identity processing is required to produce priming.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.66-68
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• 2022

활용도가 높아지고 있는 최근의 딥러닝 애플리케이션 등을 사용하기 위해서 기존의 CPU 구조로는 한계가 있어 GPU, TPU 등의 하드웨어로 가속하려는 노력이 있어왔다. 하지만 물리적인 제약으로 인해 메모리 대역폭에 한계가 있으며, 이를 뛰어넘기 위해 메모리 안에서 직접 연산을 수행하는 Processing-in-Memory 기술이 떠오르고 있다. 본 논문은 PIM 기술을 사용할 때의 불이익을 감수하면서 장점을 최대한 활용하는 방법들에 관해서 서술하였다.

• Journal of Information Processing Systems
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• v.2 no.3 s.4
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• pp.147-152
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• 2006

NAND flash memory-based embedded systems are becoming increasingly common. These embedded systems have to provide a fast boot time. In this paper, we have designed and proposed a flash file system for embedded systems that require fast booting. By using a Flash Image Area, which keeps the latest flash memory information such as types and status of all blocks, the file system mounting time can be reduced significantly. We have shown by experiments that our file system outperforms YAFFS and RFFS.