• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.157.5-157
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• 2001

Generally, the application of Programmable Logic Controller PLC is emphasized on the Process Control. This paper presents Neurofuzzy application, Which can estimate the distance to a fault by means of PLC and based up on the Electrical Power System theory and ground resistance. The case study refers to the distribution lines of the Provincial Electricity Authority (PEA). Also, the thesis is supposed to be of much benefit: saving time both to go to the scene and to clear fault, reducing unpleasant impacts on customers and stabilizing reliability of the distribution lines.

• 한국통신학회논문지
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• 제21권8호
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• pp.1948-1957
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• 1996

통신 프로토콜의 적합성 시험은 구현된 프로토콜이 표준규격과 동일하게 구현되었는지를 검사하는 과정을 말한다. 생성된 시험 항목이 어느 정도의 오류를 발견해 낼 수 있는지를 평가함으로써 적합성 시험의 효율성을 평가하는 하나의 기준으로 사용될 수 있다. 시험 항목의 오류 발견 능력의 평가 방법은 주로 수학적 평가 방법과 시뮬레이션을 이용한 연구가 이루어져 왔다. 본 논문에서는 기존 평가 방법의 문제점을 지적하고 오류 모델을 사용하여 생성된 시험항목에 대한 새로운 오류 발견 평가 모델을 제시하였다. 그리고 제안된 평가 모델을 기존의 방법과 비교, 분석하여 타당성을 입증하였다.

• 대한전기학회논문지
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• 제39권10호
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• pp.1021-1028
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• 1990

본 논문은 전력계통의 고장진단 전문가시스템에 관한 것으로서 개발된 전문가 시스템은 전력계통에서의 사고 발생시 그 고장구간을 추정하고 보호기기의 오.부작동을 판정하며 이를 통하여 고장의 전파과정을 설명하도록 고안되었으며 또한 사고발생후 취하여질 복구작업에 필수적으로 요구되는 정전구역의 탐색의 효율을 위하여 탐색구간을 제한하였다. 본 전문가 시스템은 포롤로그 언어를 사용하여 구성하였으며 모의계통에 적용하여 그 요 성을 입증하였다. 입증하였다.

• Tribology and Lubricants
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• 제18권2호
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• pp.117-126
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• 2002

Abstract - An integrated condition monitoring algorithm based on an expert system was implemented in this work in order to monitor effectively the machine conditions. The knowledge base was consisted of numeric data which meant the posterior probability of each measurement parameter for the representative machine failures. Also the inference engine was constructed as a series of statistical process, where the probable machine fault was inferred by a mapping technology of pattern recognition. The proposed algorithm was, through the user interface, applied for an air compressor system where the temperature, vibration and wear properties were measured simultaneously. The result of the case study was found fairly satisfactory in the diagnosis of the machine condition since the predicted result was well correlated to the machine fault occurred.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.359-362
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• 2000

In this paper, we propose a test pattern generation algorithm on the basis of the identification of undetectable faults for Speed-Independent(SI) asynchronous control circuits. The proposed methodology generates tests from the specification of a target circuit, which describes the behavior of the circuit in the form of Signal Transition Graph (STG). The proposed identification method uses only topological information of a target circuit and reachability information of a fault-free circuit, which is generated in the form of Binary Decision Diagram(BDD) during pre-processing. Experimental results show that high fault coverage over single input stuck-at fault model is obtained for several synthesized SI circuits and the use of the identification process as a preprocessing decreases execution time of the proposed test generation with negligible costs.

• 대한전기학회논문지:전력기술부문A
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• 제48권4호
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• pp.444-451
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• 1999

A diagnostic rule-base design method for enhancing fault detection and isolation performance of multiple obsever based fault detection isolation schemes (FIDS) is presented. The diagnostic rule-base has a hierarchical framework to perform detection and isolation of faults of interest, and diagnosis of process faults. The decision unit comprises a rule base and a fuzzy inference engine and removes some difficulties of conventional decision unit which includes crisp logic with threshold values. Emphasis is placed on the design and evaluation methods of the diagnostic rult-base. The suggested scheme is applied to the FDIS design for a DC motor driven centrifugal pump system.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.882-885
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• 2011

This paper presents testing and self-calibration of RF circuits using MEMS switches to identify process-related defects and out of specification circuits. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.

• Journal of information and communication convergence engineering
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• 제3권1호
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• pp.28-32
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• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2175-2177
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• 2001

This paper presents a faults diagnosis technique of induction motors based on a neural network. Only stator current is measured, transformed by using FFT and normalized for the training. Healthy, bearing fault, stator fault and rotor end-ring fault motors are prepared to obtain the learning data and diagnose the several faults. For more effective diagnosis, the load rate is changed by 100%, 60%, 30% of full load and the obtained are applied to the learning process. The experimental results show the proposed method is very detectable and applicable to the real diagnosis system.