• Korean Journal of Computational Design and Engineering
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• v.2 no.3
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• pp.161-174
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• 1997

In this paper, the techniques for graphic simulation of material removal process are described. The concepts of the bounding box and base plane are proposed. With these concepts, a real-time shaded display of a Z-map model being milled by a cutting tool following an NC path can be implemented very efficiently. The base planes make it possible to detect the visible face of Z-map model effectively. And the bounding box of tool sweep volume provides minimum area of screen to be updated. The proposed techniques are suitable for implementation in raster graphic device and need a few memories and a small amount of calculation. Proposed method is written in C and executable on MS-Windows95 and Window-NT.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.195-198
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• 2017

This research analyzed the electrical characteristics of an 80 V optimal trench power MOSFET (metal oxide field effect transistor) for mobile applications. The power MOSFET is a fast switching device in fields with low voltage(<100 V) such as mobile application. Moreover, the power MOSFET is a major carrier device that is not minor carrier accumulation when the device is turned off. We performed process and device simulation using TCAD tools such as MEDICI and TSUPREM. The electrical characteristics of the proposed trench gate power MOSFET such as breakdown voltage and on resistance were compared with those of the conventional power MOSFET. Consequently, we obtained breakdown voltage of 100 V and low on resistance of $130m{\Omega}$. The proposed power MOSFET will be used as a switch in batteries of mobile phones and note books.

• Journal of International Society for Simulation Surgery
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• v.1 no.2
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• pp.62-66
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• 2014

Image registration is the process for finding the correct geometrical transformation that brings one image in precise spatial correspondence with another image. There are limitations on the visualization of simple overlay between two different modality images because two different modality images have different anatomical information, resolution, and viewpoint. In this paper, various image registration methods and their applications are introduced. With the recent advance of medical imaging device, image registration is used actively in diagnosis support, treatment planning, surgery guidance and monitoring the disease progression.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.5
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• pp.13-20
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• 2012

The light transmittance of optical device is one of the important conditions to improve the product performance and it has researched through the various methods. One of these methods to improve the optical transmittance is to use a pattern on optical surface. The advantages of this method are to simplify the manufacturing process and to easy mass production. If a surface of glass has with the proper patterns, we can expect a great effect on optical transmittance. The purpose of this research is to derive a pattern to get high transmittance from a theoretical approach and to analyze the transmittance through the simulation. And then, we made a sample with a pattern and compared with the results from simulation and experiment.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.182-192
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• 2003

A new Monte Carlo (MC) simulator for electron beam lithography process in the multi-layer resists and compound semiconductor substrates has been developed in order to fabricate and develop the high-speed PHEMT devices for millimeter-wave frequencies. For the accurate and efficient calculation of the transferred and deposited energy distribution to the multi-component and multi-layer targets by electron beams, we newly modeled for the multi-layer resists and heterogeneous multi-layer substrates. By this model, the T-shaped gate fabrication process by electron beam lithography in the PHEMT device has been simulated and analyzed. The simulation results are shown along with the SEM observations in the T-gate formation process, which verifies the new model in this paper.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.286-289
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• 1991

We simulated ion implantation and annealing condition of 1 ${\mu}m$ CMOS device using process simulator, SUPREM-II. In this simulation, optimal condition of ion implantation for symmetric threshold voltage determination of PMOS and NMOS region, junction depth and sheet resistance of source/drain region, impurity profile of each region are investigated. Ion implantation dose for 3 ${\mu}m$ N-well junction depth and symmetric threshold voltage of $|0.6|{\pm}0.1$ V were $1.9E12Cm^{-2}$(for phosphorus), $1.7E122Cm^{-2}$(for boron) respectively. Also annealing condition for dopant activation are examined about $900^{\circ}C$, 30 minutes. After final process step, N-well junction, P+ S/D junction and N+ S/D junction depth are calculated 3.16 ${\mu}m$, 0.45 ${\mu}m$ and 0.25 ${\mu}m$ respectively.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.1
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• pp.14-17
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• 2005

In this paper, an automated methodology for generating model parameters considering real manufacturing processes is presented with verified results. In addition, the outcomes of applications to the next generation of flash memory devices using the parameters calibrated from the process specification decision are analyzed. The test vehicle is replaced with a well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for a flash memory device. The calibration errors are less than 5% of a full chip operation, which is acceptable to designers. The results of the calibration are then used to predict the I-V curves and the model parameters of various transistors for the design of flash devices.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.50-56
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• 2022

In order to process a vast amount of data, there is demand for a new system with higher processing speed and lower energy consumption. To prevent 'memory wall' in von Neumann architecture, RRAM, which is a neuromorphic device, has been researched. In this paper, we summarize the features of RRAM and propose the device structure for characteristic improvement. RRAM operates as a synapse device using a change of resistance. In general, the resistance characteristics of RRAM are nonlinear and random. As synapse device, linearity and uniformity improvement of RRAM is important to improve learning recognition rate because high linearity and uniformity characteristics can achieve high recognition rate. There are many method, such as TEL, barrier layer, NC, high oxidation properties, to improve linearity and uniformity. We proposed a new device structure of TiN/Al doped TaO_x/AlO_x/Pt that will achieve high recognition rate. Also, with simulation, we prove that the improved properties show a high learning recognition rate.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2407-2409
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• 2005

As the cumulative amount of spent fuel increases, the reliable and effective management of the spent fuel has become a world-wide mission. For this mission, KAERI is developing the Advanced Spent Fuel Conditioning Process (ACP) as a pre-disposal treatment process for spent fuel. Conventional approach to the development of the process and the remote operation technology is to fabricate the process equipment on the same scale as the real environment and demonstrate the remote handling operation using simulated fuel called a mock-up test. But this mock-up test is expensive and time consuming, since the design may need to be modified and the equipment fabricated again to account for the problems found during a testing. To deal with this problem, we developed a digital mockup for the ACP. Also, for an effective utilization of the digital mockup, we developed user interface modules such as the data acquisition and display module and the external input device interface module. The result of this implementation shows that a continuous motion of the manipulator using the external device interface can be represented easily and the information display screens responded well to the simulation situation.