• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.4
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• pp.49-56
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• 2021

This paper describes the modeling and simulation of a four-axis dedicated robot that can attach and detach a workpiece on a computer numerical control (CNC) lathe. The robot was modeled as a Scarab robot for compatibility with CNC lathes. The advantages of such a robot are that an actuator with a small capacity can be used for the robot and the degrees of freedom of the robot can be reduced to four. For the simulation of the four-axis dedicated robot, a regular kinematic equation and an inverse kinematic equation were derived. Simulations were performed with these equations from the position of the loading device to the chuck position of the lathe before machining and from the chuck of the lathe to the position of the loading device after machining. The simulation results showed that the four-axis dedicated robot could be operated accurately, and they provided the joint angle of each motor (θ1, θ2, and θ3).

• Korean Journal of Materials Research
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• v.18 no.5
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• Journal of the Semiconductor & Display Technology
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• v.11 no.1
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• pp.49-54
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• 2012

There have been plenty of difficulties because properties of Alq3 are unable to acquire in a process of manufacture of OLED. In this paper it will predict a viscosity of Alq3 through DSMC technique and suggest the way regarding a study to estimate properties of material through the computer simulation. There could generate errors of a simulation process in a vacuum deposition process since the properties of material that is used in a high-degree vacuum environment are not secured. Therefore, we would like to propose the new methods that can not only predict properties of a molecular unit but also raise an accuracy of simulation process by forecasting properties of Alq3.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.157-165
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• 2001

We analyzed the electrical characteristics of platinum silicide schottky junction to develope the voltage swing in Integrated Schottky Logic gates, and simulated the characteristics with the programs in this junctions. Simulation programs for analytic characteristics are the Medichi tool for device structure, Matlab for modeling and SUPREM V for fabrication process. The silicide junctions consist of PtSi and variable silicon substrate concentrations in ISL gates. Input parameters for simulation characteristics were the same conditions as process steps of the device farications process. The analitic electrical characteristics were the turn-on voltage, saturation current, ideality factor in forward bias, and has shown the results of breakdown voltage between actual characteristics and simulation characteristics in reverse bias. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height were decreased but saturation current and ideality factor were increased by substrates increased concentration variations.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.946-949
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• 1999

In this research we have developed a reliable, effective and feasible HEI(High-Energy Ion Implantation) process 3D-simulation tool, and then by using it we can predict and analyze the effect of HEI process on characteristics of the standard CMOS device. high-energy ion implantation above 200 keV is inevitable process to form retrograde well and buried layer to prevent leakage current, to conduct field implant for field isolation, and to perform after-gate implantation. The feasible analysis tool is a product of the HEI process modeling verified by comparison of the SIMS experiments with the simulation results. Especially, in this paper, we present the predicting capability of HEI-induced impurity and damage profiles compared with the published SIMS data in order to acquire the reliability of our results ranging from few keV to several MeV for phosphorus and boron implantation.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Elastomers and Composites
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• v.53 no.4
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• pp.226-233
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• 2018

Elastomers based on the thermoplastics are widely used in rubber industries. Thermoplastic elastomers have the advantages of an easy shaping process and elimination of recycling problems. Thermoplastic polyester elastomer (TPE) is used for making rubber bands in wearable devices and its applications are increasing. In this study, five wrist bands were designed and their mechanical behaviors were examined by computer simulation, using hyper elastic models, Mooney-Rivlin and Ogden models, and a linear elastic model. Simulation results were compared and discussed in terms of band design and material model.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.561-564
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• 1998

This paper describes a performance degradation of static type input buffer due to the device degradation in menory devices using $0.8\mu\textrm{m}$ CMOS process. experimental results shows that the degradation of MOS device affects the Trip Point shift in static type input buffer. We have performed the spice simulation and calculated the Trip Point with model parameter and measurement data so that how much the Trip Point(VLT) variate.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.537-540
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• 1998

A MESFET device with double $\delta-doped$ channel is designed and investigated by computer simulation. The device with optimized design parameters such as a doping ratio and a spacer thickness, shows superior performance to conventional MESFETs. The effects of the FWHM of $\delta-doped$ layers device characteristics are investigated to account for the thermal process

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.