• Title/Summary/Keyword: Process Verification

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GTS-Visual Logic: Visual Logic and Tool for Analysis and Verification of Secure Requirements in Smart IoT Systems (GTS-VL: 스마트 IoT에서 안전 요구사항 분석과 검증을 위한 시각화 논리 언어 및 도구)

  • Lee, SungHyeon;Lee, MoonKun
    • KIPS Transactions on Computer and Communication Systems
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    • v.11 no.9
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    • pp.289-304
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    • 2022
  • It is necessary to apply process algebra and logic in order to analyze and verify safety requirements for Smart IoT Systems due to distributivity and mobility of the systems over some predefined geo-temporal space. However the analysis and verification cannot be fully intuitive over the space due to the fact that the existing process algebra and logic are very limited to express the distributivity and the mobility. In order to overcome the limitations, the paper presents a new logic, namely for GTS-VL (Geo-Temporal Space-Visual Logic), visualization of the analysis and verification over the space. GTS-VL is the first order logic that deals with relations among the different types of blocks over the space, which is the graph that visualizes the system behaviors specified with the existing dTP-Calculus. A tool, called SAVE, was developed over the ADOxx Meta-Modeling Platform in order to demonstrate the feasibility of the approach, and the advantages and practicality of the approach was shown with the comparative analysis of PBC (Producer-Buffer-Consumer) example between the graphical analysis and verification method over the textual method with SAVE tool.

Design and Implementation of Co-Verification Environments based-on SystemVerilog & SystemC (SystemVerilog와 SystemC 기반의 통합검증환경 설계 및 구현)

  • You, Myoung-Keun;Song, Gi-Yong
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.4
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    • pp.274-279
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    • 2009
  • The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

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A Study on Feature Extraction of Morphological Shape Decomposition for Face Verification (얼굴인증을 위한 형태학적 형상분해의 특징추출에 관한 연구)

  • Park, In-Kyu;Ahn, Bo-Hyuk;Choi, Gyoo-Seok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.9 no.2
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    • pp.7-12
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    • 2009
  • The new approach was proposed which uses feature extraction based on fuzzy integral in the process of face verification using morphological shape decomposition. The centre of area was used with image pixels related with structure element and its weight in an attempt to consider neighborhood information. Therefore the morphological operators were defined for feature extraction. And then the number of decomposition images were more about 4 times than the conventional. Finally in the simulations with the extractions for face verification it was proved that the approach in this paper was even more good than the conventional in stability of feature extraction and threshold value.

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Development of KOMPSAT-2 Vehicle Dynamic Simulator for Attitude Control Subsystem Functional Verification

  • Suk, Byong-Suk;Lyou, Joon
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1465-1469
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    • 2003
  • In general satellite verification process, the AOCS (Attitude & Orbit Control Subsystem) should be verified through several kinds of verification test which can be divided into two major category like FBT (Fixed Bed Test) and polarity test. And each test performed in different levels such as ETB (Electrical Test Bed) and satellite level. The test method of FBT is to simulate satellite dynamics with sensors and actuators supported by necessary environmental models in ETB level. The VDS (Vehicle Dynamic Simulator) try to make the real situation as possible as the on-board processor will undergo after launch. The purpose of FBT test is to verify that attitude control logic function and hardware interface is designed as expected with closed loop simulation. The VDS is one of major equipments for performing FBT and consists of software and hardware parts. The VDS operates in VME environments with target board, several commercial boards and custom boards based on the VxWorks real time operating system. In order to make time synchronization between VDS and satellite on-board processor, high reliable semaphore was implemented to make synchronization with the interrupt signal from on-board processor. In this paper, the real-time operating environment used on VDS equipment is introduced, and the hardware and software configurations of VDS summarized in the systematic point of view. Also, we try to figure out the operational concept of VDS and AOCS verification test method with close-loop simulation.

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A Reliability Verification of Screening Time Prediction Reporting of 'Cine-Hangeul'

  • Jeon, Byoung-Won
    • Journal of Multimedia Information System
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    • v.7 no.2
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    • pp.141-146
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    • 2020
  • Cine-Hangeul is a program that can predict the running time of a movie based on the screenplay before production. This paper seeks to verify the prediction reporting function of Cine-Hangeul, which is the standard Korean screenplay format. Moreover, this paper presents a method to increase the accuracy of the Cine-Hangeul reporting function. The objective of this paper is to offer a correction method based on scientific evidence because the current Cine-Hangeul reporting function has many errors. The verification process for five scenarios and movies confirmed that the default setting value of Cine- Hangeul's screening time prediction reporting was many errors. Cine-Hangeul analyzes the amount of textual information to predict the time of the scene and the time of the dialogue and helps predict the total time of the movie. Therefore, if a certain amount of text information is not available, the accuracy is unreliable. The current Cine-Hangeul prediction report confirms that the efficiency is high when the scenario volume is about 90 to 100 pages. As a result, prediction of screening time by Cine-Hangeul, a Korean scenario standard format program, confirmed the verification that it could secure the same level of reliability as the actual screening time by correcting the reporting settings. This verification also affirms that when applying about 50 percent of the basic set of screening time reporting, it is almost identical to the screening time.

Verification method and Simulation of Object model Converted to Formal Specification (형식명세로 변환된 객체모델의 검증방법과 시뮬레이션)

  • Lim, Keun
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.6
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    • pp.123-130
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    • 2007
  • In this paper, We define convert rules from objects and relation presented in object model to the state and operation domain in formal specification. Namely, object and relation in information model converted to state domain in formal specification. State, event and behavior converted to operation domain. And that way informal object model change to formal language, it can be verify through formal method. Verification process make an offer convenience and confidence in software development early phase. And we implement simulation tool in order to verification method of formal specification and to consistency verified model between user's requirement. It is possible to select the suitable model and reduce the costs and efforts on software development.

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Implementation of Advanced Dynamic Signature Verification System (고성능 동적 서명인증시스템 구현)

  • Kim, Jin-Whan;Cho, Hyuk-Gyu;Cha, Eui-Young
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.462-466
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    • 2005
  • Dynamic (On-line) signature verification system consists of preprocessing, feature extraction, comparison and decision process for internal processing, and registration and verification windows for the user interface. We describe an implementation and design for an advanced dynamic signature verification system. Also, we suggest the method of feature extraction, matching algorithm, efficient user interface and an objective criteria for evaluating the performance.

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Laboratory Test Method for the Forward Motion Compensation of Airborne Camera (항공용 카메라 전방운동 보상기능의 실험실 입증방안)

  • Song, Dae-Buem;Yoon, Yong-Eun
    • Journal of the Korea Institute of Military Science and Technology
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    • v.15 no.4
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    • pp.507-512
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    • 2012
  • Image blurring in airborne camera can be prevented through timely actuation of LOS(Line of Sight) into the opposite direction to the aircraft advancement, i.e. FMC(Forward motion compensation). Performance verification of FMC requires installation of camera to the aircraft. However, in many ways the verification process has little choice but to be implemented in the laboratory. In this paper verification method of FMC performance in the laboratory is introduced. With collimator target installed in the known reference position image obtained by actual mission plan naturally displays image blurring as well as LOS displacement by FMC effect. Through comparison of the amount of those image blurring and LOS displacement to the equivalent image distortion expected by the application of the FMC reference command can the performance be verified. In this paper we propose a new verification method of FMC performance in laboratory along with generalized solution of FMC reference command, and assess the validity of our proposition.

Methodology of CO2 Emission Factor Verification and Quantitative Assessment in Ethylene Product Processes (에틸렌 생산에서의 CO2 국가배출계수 검증 및 정량평가 방법론)

  • Youk, Soo Kyung;Jeon, Eui-Chan;Yoo, Kyung Seun
    • Journal of Climate Change Research
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    • v.9 no.1
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    • pp.69-74
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    • 2018
  • The purpose of this study is to suggest the methodology of $CO_2$ Emission Factor Verification and Quantitative Assessment in Ethylene Product Processes. At first, this study compare the IPCC (Intergovernmental Panel on Climate Change) 1996 Guideline and 2006 Guideline. And analyse methodology for estimating $CO_2$ emission and $CO_2$ emission factor in Ethylene product process. Also analyse cases of estimating $CO_2$ emission factor based on material balance. Methodology of $CO_2$ Emission Factor Verification and Quantitative Assessment are following the categories proposed by GIR (Greenhouse Gas Inventory and Research Center). There are total 12 factors in 8 categories and give 5 or 10 points according to their importance. Also this study suggests necessary data of document to meet the conditions. The result would help estimate accuracy Greenhouse Gas Inventory. Also contribute to establish policy on environmental assessment, air conservation, etc.