• Journal of Power Electronics
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• v.16 no.3
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• pp.840-848
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• 2016

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.

• Nuclear Engineering and Technology
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• v.54 no.9
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• pp.3293-3298
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• 2022

Removing radioactive contaminated metal materials is a vital task during the decommissioning of nuclear power plants to reduce the cost of the post-dismantling process. The laser decontamination technique has been recognized as a key tool for a successful dismantling process as it enables a remote operation in radioactive facilities. It also minimizes exposure of workers to hazardous materials and reduces secondary waste, increasing the environmental friendless of the post-dismantling processing. In this work, we present a thorough and efficient laser decontamination approach using a single-mode continuous-wave (CW) laser. We subjected stainless steels to a surface-removal process that repetitively exposes the laser to a confined region of ~75 ㎛ at a high scanning rate of 10 m/s. We evaluate the decontamination performance by measuring the removal depth with a 3D scanning microscope and further investigate optimal removal conditions given practical parameters such as the laser power and scan properties. We successfully removed the metal surface to a depth of more than 40 ㎛ with laser power of 300 W and ten scans, showing the potential to achieve an extremely high DF more than 1000 by simply increasing the number of scans and the laser power for the decontamination of primary circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.235-244
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• 1999

This Paper proposes a new compaction algorithm for IDDQ testing in CMOS Circuits. A primary test pattern is generated by the primitive fault pattern which is able to detect GOS(gate-oxide short) and the bridging faults in an internal primitive gate. The new algorithm can reduce the number of the test vectors by decreasing the don't care(X) in the primary test pattern. The controllability of random number is used on processing of the backtrace together four ones of heuristics. The simulation results for the ISCAS-85 benchmark circuits show that the test vector reduction is more than 45% for the large circuits on the average compared to static compaction algorithms.

• The Korean Journal of Physiology and Pharmacology
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• v.26 no.2
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• pp.69-75
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• 2022

Chronic pain is induced by tissue or nerve damage and is accompanied by pain hypersensitivity (i.e., allodynia and hyperalgesia). Previous studies using in vivo two-photon microscopy have shown functional and structural changes in the primary somatosensory (S1) cortex at the cellular and synaptic levels in inflammatory and neuropathic chronic pain. Furthermore, alterations in local cortical circuits were revealed during the development of chronic pain. In this review, we summarize recent findings regarding functional and structural plastic changes of the S1 cortex and alteration of the S1 inhibitory network in chronic pain. Finally, we discuss potential neuromodulators driving modified cortical circuits and suggest further studies to understand the cortical mechanisms that induce pain hypersensitivity.

• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.73-81
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• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.94-103
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• 1994

In testing for practical scan disigned logic circuits, there may exist logic value constraints on some part of primary inputs due to various requirements on design and test. This paper presents a logic value system called taboo logic values which targets the test pattern generation of logic circuits under logic value constraints. The taboo logic system represents the logic value constraints and identifies additional logic value constraints through the implication of the tqaboo logic values using a taboo logic calculus. Those identified logic value constraints will guide the search during the test pattern generation of avoid the unfruitful searches and to identify redundant faults due to the logic value constraints very quickly. Finally, experimental results on ISCAS85 benchmark circuits will demonstrate the efficiency of the taboo logic values.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.9-12
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• 2008

Mathematical singularities of circuit equations with three-phase ideal transformer connections are studied. Three-wired wye-wye connections, delta-delta connections, and primary four-wired wye-delta connections are singular. The matrices of their circuit equations have zeros in their eigenvalues. Three-wired wye-delta connections, wye-wye-delta connections, and primary four-wired wye-wye connections are not singular. The physical meaning of their singularities is that they are sensitive and prone to be ill-conditioned. Equivalent shunt admittances representing ion losses and magnetizing inductances make the singular matrices non-singular in wye-connected circuits. And, equivalent series impedances representing copper losses and leakage inductances make the singular matrices non-singular in delta-connected circuits. The tableau analysis is used for the study.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.17-22
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• 1974

In this paper, the problem of finding tests to detect faults in combinational logic circuits is considered. At first, the method of fault detection in fan-out-free irredundant circuits is derived, and the result is extended to the fan-out redundant circuits. A fan-out circuit is decomposed into a set of fan-out-free subcircuits by cutting the lines at the internal fan-out points, and the minimal detecting test. sets for each subcircuit are found separately. And then, the compatible tests from each test set are combined maximally into composite tests to generate primary input binary vectors. By this procedure. the minimal complete test sets for reconvergent fan-out circuits are easily found and the detectable and undetectable faults are also classified clearly.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.63-70
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• 1994

In this paper, we propose a fault simulation method based on primary output in combinational circuit. In the deterministic test pattern generation, each test pattern is genterated incrementally. The test pattern is applied to the primary inputs of circuit under test to simulate faults. We detect the faults with respect to each primary output. The fault detection with resptect to each primary output is reflected by the corresponding bit in the detection words, and efficient fault detection for the reconvergent fan-out stem is achieved with dynamic fault propagation. As an experimental result of the fault simulation with our method for the several bench mark circuits, we illustrated the good performance showing that the number of gates to be activated is much reduced as compared with other method which is not based on primary output.