• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.102-112
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• 2005

In this work, we developed fully integrated broadband MMIC chip set employing CSP(Chip Size Package) for K/Ka band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. $STO(SrTi_{3})$ capacitors were employed to integrate the DC biasing components on the MMIC, and LC parallel circuits were employed for DC feed and ESD protection. A pre-matching technique and RC parallel circuit were used to achieve a broadband matching and good stability fer the amplifier MMIC in K/Ka band. The amplifier CSP MMIC exhibited good RF performance over a wide frequency range in K/Ka band. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the K/Ka band.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.11
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• pp.2479-2485
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• 2013

In this paper, we present a design for solid-state radar SSPA with sequential bias. We apply to variable extension pulse generator to eliminate signal distortion which is caused by bias rising/falling delay of power amplifier. There is an optimum impedance matching circuit to have high efficiency of GaN-power device by measuring microwave characteristics through load-pull method. The designed SSPA is consisted of pre-amplifier, drive-amplifier and main-amplifier as a three stages to apply for X-Band solid-state radar. Thereby we made a 200W SSPA which has output pulse maximum power shows 53.67dBm and its average power is 52.85dBm. The optimum design of transceiver module for solid-state pulse compression radar which is presented in this dissertation, it can be available to miniaturize and to improve the radar performances through additional research for digital radar from now on.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.39-44
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• 2005

The OFDM modulation and transmission block have been modeled in order to analyse the relationship between the 2.4GHz power amplifier distortion and output ACPR for the IEEE 802.11g wireless LAN. The nonlinear characteristic of the power amplifier has been modeled as AM-to-AM and AM-to-PM using the behavioral model, and the output spectrum is analysed with the phase distortion variation. Also, amplifier back-off value from P1dB to satisfy the required IEEE 802.11g standard spectrum mask s been simulated with modeled phase distortion, and the simulation data have been compared to the measured result by using the pre-distortion technique.

• Korean Journal of Optics and Photonics
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• v.5 no.1
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• pp.166-172
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• 1994

The fiber optic receiver, ETRI APD-FET 1.0, is developed for the application of optical communication. This fiber optic receiver includes PD sub-module and pre-amplifier case. A single lens system is introduced for the PD sub-module. The sub-module consists of the avalenche photodiode(APD), GRIN rod lens, and a single mode fiber. The above components are enclosed into the stainless steel 304L housings. By bevelling the fiber end, the single mode fiber provides less than ~ 28 dB of optical return loss. The area of image focus is controlled by adjusting the length of spacer located in-between the fiber and the GRIN rod lens. The laser welding technique is applied to achieve the maximum coupling efficiency for the joining of each housing. In the pre-amplifier case, GaAs FET pre-amplifier workes for photocurrent amplification and the thermister is mounted to control the APD bias. The performance of ETRI APD-FET1.0 shows the sensitivity of - 30.3 dBm at $10^{-10}$ BER(bit error rate) and 2.5 Gbps optical random signal of $2^{23}-1$ word length. The fiber optic receiver is one of the essensial parts of the transmission module for B-ISDN. Also, the above optical packaging technology will be adapted for the developement of 10 Gbps transmission application 2.5 Gbps 5 Gbps

• The Journal of Information Technology
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• v.10 no.3
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• pp.77-92
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• 2007

This study aims to suggest an implementation methodology of security module for data integrity of mobile internet terminal. This is based on the WTLS(Wileless Transport Layer Security) of WAP Protocol. This security module is expected to achieve central role in conversion of wireless internet environment and emphasis of encryption technology and safe and calculable wireless communication environment construction.

• Journal of Biomedical Engineering Research
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• v.9 no.2
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• pp.179-184
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• 1988

In this study, we improve the performance of telemetry ECG modem using acoustic coupler. The results are as follows : (1) General active filter is replaced by SCF(switched capaciror filter) improving the LPF and BPF characteristics. (2) ECG Pre-amplifier is installed in ECG modem. (3) The interface circuit is designed to store the ECG waveform in casette recorder.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.24-36
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• 2003

The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1079-1086
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• 2012

In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.561-567
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• 2017

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

• Journal of Multimedia Information System
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• v.8 no.2
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• pp.143-146
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• 2021

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.