• 대한의용생체공학회:의공학회지
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• 제16권3호
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• pp.301-308
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• 1995

A high-precision pre-amplifier is designed for general use in EEG measurement system. It consists of signal generator, signal amplifier with a impedance converter, shield driver, body driver, differential amplifier, and isolation amplifier. The combination of minimum use of inaccurate passive components and the appropriate matching of each monolithic amplifiers results in good noise behavior, low leakage current, high CMRR, high input impedance, and high IMRR. The performance of EEG pre-amplifier has been verified by showing the typical EEG pattevn of a nomad person through the clinical experiments.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.409-412
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• 2000

A high performance EEG signal measurement system is fabricated. It consists of high precision pre-amplifier and auto identification bandwidth unit. High precision pre-amplifier is composed of signal generator, signal amplifier with a impedance converter, body driver and isolation amplifier. The pre-amplifier is designed for low noise characteristics, high CMRR, high input impedance, high IMRR and safety, Auto identification bandwidth unit is composed of AD-converter and PIC micro-controller for real time processing EEG signal. The performance of EEG signal measurement system has been shown the classified bandwidth through the clinical demonstrations.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권11호
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• pp.550-556
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• 2001

The computerized cardiac analysis system, which acquires and analyzes the electrical activation signal propagating along the surface of the heart, is indispensible equipment for the open heart surgery and electrical cardiac study. In this paper, the design requirement and the electrical circuit analysis are performed to construct the multi-channel cardiac activation pre-amplifier necessary for a signal conditioning circuit. The general 64 channel configuration is expanded into 128 channels to enhance the spatial resolution on the mapped surface of the heart. The 128 channels pre-amplifier consists of input circuit, differential amplifier, right leg driven circuit and isolation part. It has distinct features; high voltage protection, leakage current limitation, isolation and the maximization of common mode rejection ratio with respect to the half-cell potential difference due to different electrode materials. The final pre-amplifier circuit is assembled with 8 boards, each of which composing of 16 channels.

• 한국정보통신학회논문지
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• 제9권7호
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• pp.1529-1533
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• 2005

본 논문에서는 광대역전력증폭기에 사용가능한 전치증폭기를 설계하였다. 전치증폭기는 주파수특성과 잡음특성이 우수한 WJ사의 AMl의 사용하였다. 부궤환을 이용하여 100MHz${\~}$3GHz 대역에 걸쳐서 우수한 VSWR 특성과 주파수 특성을 갖도록 설계하였다. 설계된 전치증폭기는 EMC 측정장비와 같은 광대역 i성을 필요로 하는 장비의 전력 증폭기에 활용 가능할 것으로 사료된다.

• 전기학회논문지
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• 제58권8호
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• pp.1572-1579
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• 2009

In this dissertation ultra-broadband power amplifier(UPA) was designed and fabricated using negative feedback technique. UPA was made of pre-amplifier, drive amplifier and power amplifier. Negative feedback technique was used to achieve ultra-broadband performance. Designed power amplifier has 30dB gain and 2W output power. The load-pull data of power amplifier for optimal power matching was extracted from the measured S-parameter. Fabricated PCB material, permittivity is 4.6 and thickness is 0.8mm, is FR4 and UPA was fabricated 3 modules for comparison of the simulated and measured results. Size of the fabricated pre-amplifier and drive amplifier module is 40mm'50mm'16mm. And from the experimental results, gain of the pre-amplifier module is 9.87dB at 2GHz and flatness is 0.63dB. Experimental result of the drive amplifier module is 10.97dB at 2GHz and flatness of that is 0.26dB. Test result of the power amplifier module is 10.71dB at 2GHz and flatness is 0.72dB. Total size of the power amplifier is 45mm'134mm'16mm. According to the test results, gain of the UPA is 28.98dB at 2GHz and flatness is 1.68dB. Output power was 32.098dBm at 2GHz, 32.154dBm at 1GHz and 31.273dBm at 100MHz.

• 대한전자공학회논문지TC
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• 제44권4호
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• pp.65-71
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• 2007

Doherty 전력증폭기는 일반전력증폭기보다 효율은 뛰어나지만 많은 왜곡성분이 발생한다. 이러한 왜곡성분은 일반적인 진폭왜곡과 위상왜곡, 그리고 메모리 효과에 의한 왜곡성분으로 구분할 수 있다. 본 논문에서는 전기적인 비선형성을 정확히 모델링하고 열 메모리 효과가 Doherty 증폭기에 미치는 영향을 연구함으로써, 전치왜곡기에 적용할 수 있는 열 메모리 효과 보상기를 제안하였다. Doherty 증폭기의 열 메모리 특성을 모델링하기 위하여 순시적으로 소모되는 전력과 순시 접합온도의 정확한 관계식을 정립하여 제안하였다. 제안된 모델의 파라미터는 전치왜곡기를 사용한 Doherty 증폭기의 열 메모리효과를 효율적으로 억제한다. 이러한 열 메모리 보상기를 가진 전치왜곡기는 선형화된 전력증폭기의 출력스펙트럼에서 약 22 dB정도의 ACLR 개선효과를 보인다. 측정결과는 50W급 LDMOS Doherty 전력증폭기로 측정하였으며, 열 메모리 보상기를 가진 전치왜곡기는 ADS로 검증하였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.485-488
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• 2005

본 논문에서는 광대역전력증폭기에 사용가능한 전치증폭기를 설계하였다. 설계된 전치증폭기는 주파수 특성과 잡음특성이 우수한 WJ사의 AM1을 사용하였다. 부궤환을 이용하여 100MHz ${\sim}$ 3GHz 대역에 걸쳐서 우수한 VSWR 특성과 주파수 특성을 갖도록 설계하였다.

• IEIE Transactions on Smart Processing and Computing
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• 제4권4호
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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• pp.218-222
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• 2008

RF power amplifier requires linearization in order to reduce adjacent channel interference. And most of the existing linearization algorithms assume that a PA has memory-less nonlinearity. But for the wider bandwidth signal, the memory effect of PA cannot be ignored. This paper investigates digital pre-distortion by use of a memory polynomial model which compensates for amplifier nonlinearity and memory effect. The look-up table based implementation scheme is used to reduce the computational complexity of the pre-distortion block. The linearization performance is demonstrated on wideband CDMA signal and class AB high power amplifier.

• 전자공학회논문지D
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• 제34D권3호
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• pp.52-59
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• 1997

Design and performance of principal four ICs for the 10-Gb/s optical communication system are presented. AlGaAs/GaAs HBTs are basic devices to implement a laser diode driver, apre-amplifier, and a limiting amplifier, and GaInP/GaAs HBTs are used for an AGC amplifier. We fbricated 11.5-GHz LD driver, a pre-amplifier, and a limiting amplifier, an dGaInP/GaAs HBTs are used for an AGC amplifier. We fabricated LD deriver, 10.5 GHz pre amplifier, 7.2 GHz AGC amplifier, and 10.3 GHz limiting amplifier, optimized circuit design and the stabilized MMIC fabrication process.