• Title/Summary/Keyword: Power supply noise

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Development of Equipment and Process on Dry Ice Blasting (드라이아이스 펠렛 세정 장치 및 공정개발)

  • Park, Jong Soo;Kim, Hotae;Kim, Sun-Geon
    • Clean Technology
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    • v.10 no.3
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    • pp.121-130
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    • 2004
  • Pelletizer of dry ice snow produced by adiabatic expansion of liquid carbon dioxide and their blaster were designed and manufactured. The blaster had a high cleaning power against various contaminants on the surface such as stain, oily dirt, lacquer film and paints with low blasting pressure and low consumption of blasting air. The capacity of hopper for dry ice pellet supply was 12 kg and the mass rate of pellet blasting was controlled in 0 to 1.2 kg/min. The impact of the pellets was independent of standoff distance within a certain limiting distance, and dependent on the impact stress, angle and mass rate of dry ice pellet blasting. On the other hand the cleaning power was influenced by thermal properties and surface roughness of the substrates and decreased in the order of glass, copper, brass, steel and acryl. The power was also affected by hardness and adhesion of the contaminant on the substrate, and decreased in the order of grease, epoxy and paint. The noise was detected during blasting in the range of 85 to 100dBA.

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Design of Stack Monitoring System with Improved Performance (성능이 향상된 Stack Monitoring System의 설계)

  • Jang, Kyeong-Uk;Lee, Joo-Hyun;Lee, Seong-Won;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.20 no.3
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    • pp.299-302
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    • 2016
  • In this paper, we designed the stack monitoring system with improved performance. To block the incoming pulse noise to the amplifier, shield and the power supply impedance are reduced and the power circuit is isolated. The control unit is developed with variable high voltage, adaptive gain, offset and threshold in order to match the scintillation detector characteristic to the apparatus. 300-1500V variable high voltage power circuit is configured applicable to various scintillation detector. Stack monitoring system with improved performance guarantee the efficiency and the reliability by considering the characteristic of various scintillation detector. Developed stack monitoring system is evaluated with certified testing equipment and shows excellent performance with respect to the uncertainty of the sensor test results.

Analysis of Tank Oscillation Voltages of Sub-1V Series Tuned Varactor-Incorporating Balanced Common-Gate and Common-Drain Colpitts-VCO (서브-1V 직렬공진 바렉터 통합형 평형 공통 게이트와 공통 드레인 콜피츠 전압제어 발진기의 탱크 발진전압에 대한 해석)

  • Jeon, Man-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.7
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    • pp.761-766
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    • 2014
  • This study performs the analytical investigation of the oscillation voltages at the tanks of the series tuned varactor incorporating balanced common-drain, and common-gate Colpitts VCO which are able to work even at the sub-1V power supply voltages. The results the investigation predicts is verified by the simulation on the circuit behaviors of the two VCOs. The analytical investigation finds that the series tuned varactor incorporating balanced common-gate VCO generates greater oscillation voltage at the tank than the series tuned varactor incorporating balanced common-drain VCO does, which in turn is more suitable for generating the low phase noise oscillation signal from the sub-1V supply voltage than the series tuned varactor incorporating balanced common-drain VCO.

A Fully-Integrated Low Phase Noise Multi-Band 0.13-um CMOS VCO using Automatic Level Controller and Switched LC Tank (자동 크기 조절 회로와 Switched LC tank를 이용한 집적화된 저위상 잡음 다중 대역 0.13-um CMOS 전압 제어 발진기)

  • Choi, Jae-Won;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.1
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    • pp.79-84
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    • 2007
  • In this paper, a fully-integrated low phase noise multi-band CMOS VCO using automatic level controller (ALC) and switched LC tank has been presented. The proposed VCO has been fabricated in a 0.13-um CMOS process. The switched LC tank has been designed with a pair of capacitors and two pairs of inductors switched using MOS switch. By using this structure, four band (2.986 ${\sim}$ 3.161, 3.488 ${\sim}$ 3.763, 4.736 ${\sim}$ 5.093, and 5.35 ${\sim}$ 5.887 GHz) operation is achieved in a single VCO. The VCO with 1.2 V power supply has phase noise of -118.105 dBc/Hz @ 1 MHz at 2.986 GHz and -113.777 dBc/Hz @ 1 MHz at 5.887 GHz, respectively. The reduced phase noise has been approximately -1 ${\sim}$ -3 dBc/Hz @ 1 MHz in the broadest tuning range, 2.986 ${\sim}$ 5.887 GHz. The VCO has consumed 4.2 ${\sim}$ 5.4 mW in the entire frequency band.

Post-Linearization Technique of CMOS Cascode Low Noise Amplifier Using Dual Common Gate FETs (두 개의 공통 게이트 FET를 이용한 캐스코드형 CMOS 저잡음 증폭기의 후치 선형화 기법)

  • Huang, Guo-Chi;Kim, Tae-Sung;Kim, Seong-Kyun;Kim, Byung-Sung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.7 s.361
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    • pp.41-46
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    • 2007
  • A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

Design of a CMOS LNA for MB-OFDM UWB Systems (MB-OFDM 방식의 UWB 시스템을 위한 CMOS LNA 설계)

  • Lee Jae-kyoung;Kang Ki-sub;Park Jong-tae;Yu Chong-gun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.1
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    • pp.117-122
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    • 2006
  • A CMOS LNA based on a single-stage cascode configuration is designed for MB-OFDM ultra-wide band(UWB) systems. Wideband($3.1GHz\~4.9GHz$) input matching is performed using a simple bandpass filter to minimize the chip size and the noise figure degradation. The simulation results using $0.18{\mu}m$ CMOS process parameters show a power gain of 9.7dB, a 3dB band width of $2.1GHz\~7.1GHz$, a minimum NF of 2dB, an IIP3 of -2dBm. better than -11.8dB of input matching while occupying only $0.74mm^2$ of chip area. It consumes 25.8mW from a 1.8V supply.

The Ozone Generation and Discharge Noise Characteristics of Superposed Discharge Noise Characteristics of Superposed Discharge Type Ozonizer Using Three-Phase Voltage (3상 전압을 사용한 중첩방전형 오존발생기의 오존생성 및 방전잡음특성)

  • 전병준;송현직;김영훈;최상태;이광식
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.14 no.2
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    • pp.59-67
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    • 2000
  • In this paper, an ozonizer, which can supply individual and superposed silent discharge using three-phase voltage has been designed and manufactured. The ozonizer consists of 3 electrodes(Central Electrode, Internal Electrode and External Electrode and External electrode) and 2 gaps (gap between Central Electrode and Internal Electrode, gap between Internal Electrode and External Electrode). Ozone is generated according to voltage supplying method to each electrode by individual silent discharge and three-phase superposed discharge. The characteristics of ozone generation were investigated with variation of discharge power and the flow rate of supplied gas (O2). In case of individual silent discharge, the maximum values of ozone concentration, ozone generation and ozone yield were obtained between internal electrode and external electrode, and its values were 2300[ppm], 570[mg/h] and 745[g/kWh] respectively. Each maximum value was 5039[ppm], 1773[mg/h] and 851[g/kWh] respectively, when three-phase superposed silent discharge was employed. Therefore, characteristics of ozone generation with three-phase voltage are improved compared with single-phase voltage because silent discharge is generated continuously.

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A 2.3-2.7 GHz Dual-Mode RF Receiver for WLAN and Mobile WiMAX Applications in $0.13{\mu}m$ CMOS (WLAN 및 Mobile WiMAX를 위한 2.3-2.7 GHz 대역 이중모드 CMOS RF 수신기)

  • Lee, Seong-Ku;Kim, Jong-Sik;Kim, Young-Cho;Shin, Hyun-Chol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.51-57
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    • 2010
  • A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.

Development of a High-Performance Bipolar EEG Amplifier for CSA System (CSA 시스템을 위한 양극 뇌파증폭기의 개발)

  • 유선국;김창현;김선호;김동준
    • Journal of Biomedical Engineering Research
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    • v.20 no.2
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    • pp.205-212
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    • 1999
  • When we want to observe and record a patient's EEG in an operating room, the operation of electrosurgical unit(ESU) causes undesirable artifacts with high frequency and high voltage. These artifacts make the amplifiers of the conventional EEG system saturated and prevent the system from measuring the EEG signal. This paper describes a high-performance bipolar EEG amplifier for a CSA (compressed spectral array ) system with reduced ESU artifacts. The designed EEG amplifier uses a balanced filter to reduce the ESU artifacts, and isolates the power supply and the signal source of the preamplifier from the ground to cut off the current from the ESU to the amplifier ground. To cancel the common mode noise in high frequency, a high CMRR(common mode rejection ratio) diffferential amplifier is used. Since the developed bipolar EEG amplifier shows high gain, low noise, high CMRR, high input impedance, and low thermal drift, it is possible to observe and record more clean EEG signals in spite of ESU operation. Therefore the amplifier may be applicable to a high-fidelity CSA system.

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Implementation of Multi-layer PCB Design Simulator for Controlled Impedance (제어된 임피던스용 다층 PCB 설계 시뮬레이터 구현)

  • Yoon, Dal-Hwan;Cho, Myun-Gyun;Lin, Chi-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.73-81
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    • 2011
  • As high speed digital systems continue to use components with faster edge rate and clock speeds, transmission of the digital information, it can bring about many troubles. The increasing requirement for controlled impedance PCBs becomes both a critical success factor and a design challenge to implement a system. Especially, the noise sources in high frequency digital systems include the noise in power supply, ground and packaging, and they destroy the fidelity of signals. Therefore PCB design with impendence matching is needed to improve fidelity of signal in H/W. In this paper, we have developed an impedance control and analysis tool for multi-layer PCB design, and simulates the tracks controlled impedance with the test coupon. So, it can save the design time and support the economical PCB design.