• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.180-188
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• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• The KIPS Transactions:PartC
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• v.17C no.1
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• pp.129-134
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• 2010

Intelligent Power Switch (IPS) is a semiconductor device which contains a logic circuit in itself. It has received significant attention as a switching component to substitute the fuse and relay components in common automobile since the internal logic provides the controllability on the loads. However, a control system for the IPS status control and a network system to share the status information of IPS are required to fully exploit the capabilities of IPS. In this paper, we propose a control circuit and algorithm using IPS. Also the communication system between the control systems and IPS components using Control Area network (CAN) are proposed.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1480-1482
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• 2005

The major causes of power quality deterioration are harmonic current through semiconductor switching device, due to use of nonlinear loads such as diodes rectifier or thyristor rectifiers. In response to this concerns, this paper presents a new control method of single-phase active power filter(APF) for the compensation of harmonic current components in nonlinear loads. In order to make the complex calculation to be possible, the single-phase system that has two phases was made by constructing a imaginary second-phase giving time delay to load currents. In the conventional method, a imaginary-phase lagged to the load current T/4(here T is the fundamental cycle) was made. But in this proposed method, the new signal, which has the delayed phase through the filter, using the phase-delay property of low-pass filter, was used as the second phase. As this control method is applied to the system of single phase, an instantaneous calculation was done rather by using the rotating reference frames that synchronizes with source-frequency than by applying instantaneous reactive power theory that uses the conventional fixed reference frames.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.125-127
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• 1998

The widely used power supply (Switched Mode Power Supply : SMPS) as a source in order to stabilize direct current for electronics or communication systems has merits, when it is compared to the existing source for stability, such as high efficiency, small size, light weight by means of switching process of the semiconductor device which controls the flow of power. However, due to existence of inductors and capacitors used for charging energy, the source part in electronic or communication systems hasn't reached the speed, that is supposed to get, for achieving smaller size and lighter weight. In order to got smallness in size, it is necessary to increase switching frequency. And that makes devices for measuring energy smaller. Nevertheless, the rise switching frequency brings increases in switching loss, inductor loss, and power loss. Also, the occurrence of surge and noise caused by high frequency switching is setting higher. The resonant converter has been considered as one of methods that give solutions for the problems of SMPS and that method has been paid attention as a source technology in electronics and communication.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.472-472
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• 2011

The capacitive coupled plasma (CCP) has been extensively used in the semiconductor industry because it has not only good uniformity, but also low electron temperature. But CCP source has some problems, such as difficulty in varying the ion bombardment energy separately, low plasma density, and high processing pressure, etc. In this reason, dual frequency CCP has been investigated with a separate substrate biasing to control the plasma parameters and to obtain high etch rate with high etch selectivity. Especially, in this study, we studied on the etching of $SiO_2$ by using the pulse-time modulation in the dual-frequency CCP source composed of 60 MHz/ 2 MHz rf power. By using the combination of high /low rf powers, the differences in the gas dissociation, plasma density, and etch characteristics were investigated. Also, as the size of the semiconductor device is decreased to nano-scale, the etching of contact hole which has nano-scale higher aspect ratio is required. For the nano-scale contact hole etching by using continuous plasma, several etch problems such as bowing, sidewall taper, twist, mask faceting, erosion, distortions etc. occurs. To resolve these problems, etching in low process pressure, more sidewall passivation by using fluorocarbon-based plasma with high carbon ratio, low temperature processing, charge effect breaking, power modulation are needed. Therefore, in this study, to resolve these problems, we used the pulse-time modulated dual-frequency CCP system. Pulse plasma is generated by periodical turning the RF power On and Off state. We measured the etch rate, etch selectivity and etch profile by using a step profilometer and SEM. Also the X-ray photoelectron spectroscopic analysis on the surfaces etched by different duty ratio conditions correlate with the results above.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.45-48
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• 2013

The electronic device, such as flat panel display (FPD), is very important in our life as a means of communication between humans. Liquid crystal display (LCD), which is categorized as a flat panel display, has been used in many display products, especially in TV industry. An LED TV is composed of several electrical components, such as liquid critical module (LCM), analog to digital convertor (AD), power supplier, and inverter board. These modules are very vulnerable to particulate contamination, and causing malfunction or visibility degradation. In this study, we developed a test method for prediction of LCM's lifetime. The test system consists of carbon particle generation flame, dilution system, test chamber, and particle concentration monitoring instrument. Since the carbon particles are the most abundant in the atmosphere and easily absorb light, soot particles are used as a challenging material for this test. The concentration of generated soot particles is set around 4,000,000 #/cc, which is 400 times higher than that of usual atmospheric particles. Through this experiment, we deduced the relationship between the dust concentration and life time of the test specimen.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.131-138
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• 2011

We fabricated distributed feedback InGaAsP/InP laser diodes for optical fiber communication module and characterized the lasing properties in continuous wave operation. The active layer of 7-period InGaAsP(1.127 eV)/InGaAsP(0.954 eV) multi-quantum well structure was grown by the metal-organic chemical vapor deposition. The grating for waveguide was also fabricated by the implementation of the Mach-Zehender holographic method of two laser beams interference of He- Cd laser and the fabricated laser diode has the dimension of the laser length of $400{\mu}m$ and the ridge width of $1.2{\mu}m$. The laser diode shows the threshold current of 3.59 mA, the threshold voltage of 1.059 V. For the room-temperature operation with the current of 13.54 mA and the voltage of 1.12 V, the peak wavelength is about 1309.70 nm and optical power is 13.254 mW.

• Journal of the Semiconductor & Display Technology
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• v.6 no.1 s.18
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• pp.23-26
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• 2007

The effects of plasma treatment on the ITO/glass substrate before deposition of organic materials were investigated in the fabrication of green light emitting organic devices with $Alq_3-C545T$ fluorescent system. In our experiments, the optimum plasma treatment was obtained at the power and time of 150W and 2 minutes under the $Ar(50%)/O_2$ ambient of 1 mTorr. The green OLED with plasma treatment at 150W for 2 minutes showed the luminance and efficiency of $4700\;cd/m^2$ and 8 lm/W at 10V, respectively. On the contrary, the same structured device without plasma treatment showed much lower performance with the luminance of $2600\;cd/m^2$ and the efficiency of 3.6 lm/W at 10 V.