• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.6
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• pp.138-146
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• 2010

DC railway power supply system generally uses the running rails as negative-polarity return conductor for traction load current, and the induced rail potential and stay current cause serious problems to any electrified matter in the underground and also safety problems to human body. This paper presents a new algorithm for the analysis of the rail potential and the stray current in DC railway power system operated under independent/parallel power feeding mode. The effect of load current fluctuation during train operation is also calculated by using TPS(Train Performance Simulation) program to analysis the variation of the railway potential and stray current along railway track. Simulation program is developed based on the proposed algorithm and case studies are provided.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.5-9
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• 1998

In the high speed rail system, the distortion of the voltage and the current waveform of the input power line increases the power loss and make a several electro-magnetic problems such as EMI or the interference of the communication line. In this paper, the control scheme of the PWM converter to make a good power factor and to regulated the output voltage as well as to reduce the harmonic component of the input current is proposed. Also a control schem of the PWM converter in the parallel operation to reduce the harmonics of the input current is proposed

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1131-1136
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• 2008

The single-phase PWM converter employing power semiconductors is currently applied to the power unit of high-speed rail vehicle and increasingly used as the front-end converter with properties of near unity power factor. Power factor and harmonics are increasingly important needs for drive system of high-speed rail vehicle. The proposed approach has many advantages which include fewer semiconductor components, simplified control, high performance features and satisfies IEC 555 harmonic current standards. Simulation results show that the dc-link voltage control obey the reference value during constant load and input current is near sinusoidal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.6
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• pp.881-885
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• 2013

In this paper, we present a deterioration judgment model of urban rail power equipment using driving history, the frequency and number of failures. In addition, we have developed a deterioration judgment program based on the derived failure rate. A deterioration judgment model of power equipments on metro system was designed to establish how much environmental factors, such as thermal cycling, humidity, overvoltage and partial discharge. The deterioration rate of the transformers followed the Arrhenius log life versus reciprocal Kelvin temperature (hotspot temperature) relation. The deterioration judgment program is linked to the online condition monitoring system of urban railway system. The deterioration judgment program is based on the user interface it is possible to apply immediately to the urban rail power equipment.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1765-1768
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• 2005

Binary-search 알고리즘을 이용한 새로운 6-bit 300MS/s ADC 를 제안 하였다. 본 연구에서 제안된 ADC 는 저전력, 고속동작, 저해상도의 응용분야에 적합하도록 설계 되었다. 11 개의 rail-to-rail 비교기와 기준전압 발생기, 그리고 기준전압 제어회로로 구성 되었으며, 이는 기존의 구조와는 다른 전혀 새로운 형태로 제안된 것이다. 전력소모를 줄이기 위해 비교기 공유기술을 사용하였다. 또한 ADC 의 sub-block 인 rail-to-rail 비교기는 인버터 logic threshold 전압 값을 이용한 새로운 형태의 비교기를 제안하였다. 비교기는 인버터와 n-type preamp, p-type preamp 그리고 각각에 연결되는 latch 로 구성되었다. 기존의 rail-to-rail comparator 에 비해 입력 범위 전체 영역에서 일정한 gm 값을 얻을 수 있다. 실험결과 2.5V 공급전압에서, 17mW 의 전력 소모를 보이며, 최대 304MS/s 의 데이터 변환율을 가진다. INL 과 DNL 은 입력신호가 2.38Mhz 의 주파수를 가지는 삼각파일 때, 각각 ${\pm}0.54LSB$, ${\pm}1LSB$ 보다 작다. TSMC 0.25u 공정을 이용하였다.

• Journal of Power System Engineering
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• v.12 no.6
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• pp.5-17
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• 2008

• Journal of Power System Engineering
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• v.6 no.1
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• pp.5-11
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• 2002

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.29-36
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• 2000

The principle and design of two-stage CMOS operational amplifier with rail-to-rail input and class-AB output stage is presented. The rail-to-rail input stage shows almost constant transconductance independent of the common mode input voltage range in global transistor operation region. This new technique does not make use of accurate current-voltage relationship of MOS transistors. Hence it was achieved by using simple linear relationship of currents. The simulated transconductance variation using SPICE is less the 4.3%. The proposed global two-stage opamp can operate both in strong inversion and in weak inversion. Class AB output stage proposed also has a full output voltage swing and a well-defined quiescent current that does not depend on power supply voltage. Since feedback class- AB control is used, it is expected that this output stage can be operating in extremely low voltage. The variation of DC-gain and unity-gain frequency is each 4.2% and 12%, respectively.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.82-85
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• 2002

A compact rail to rail CMOS voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of ${\pm}$ 1.5 V. The proposed circuit has power dissipation of 5.2㎽ under quiescent condition and can drive ${\pm}$1.25 V to 250$\Omega$ load with a total harmonic distortion of less than 0.5 percent and cut off frequency of 237 ㎒. Although simple, the proposed circuit enables the output transistors to drive load efficiently.