• Title/Summary/Keyword: Power dissipation

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A Design of Novel Instrumentation Amplifier Using a Fully-Differential Linear OTA (완전-차동 선형 OTA를 사용한 새로운 계측 증폭기 설계)

  • Cha, Hyeong-Woo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.1
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    • pp.59-67
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    • 2016
  • A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

[ $8{\sim}10.9$ ]-GHz-Band New LC Oscillator with Low Phase-Noise and Wide Tuning Range for SONET communication (SONET 통신 시스템을 위한 $8{\sim}10.9$ GHz 저 위상 잡음과 넓은 튜닝 범위를 갖는 새로운 구조의 LC VCO 설계)

  • Kim, Seung-Hoon;Cho, Hyo-Moon;Cho, Sang-Bock
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.1
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    • pp.50-55
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    • 2008
  • In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

Growth of Thin Film Using Chemical Bath Deposition Method and Their Photoconductive Characteristics (CBD 방법에 의한 CdS 박막의 성장과 광전도 특성)

  • Hong, K.J.;Lee, S.Y.;You, S.H.;Suh, S.S.;Moon, J.D.;Shin, Y.J.;Jeoung, T.S.;Shin, H.K.;Kim, T.S.;Song, J.H.;Rheu, K.S.
    • Journal of Sensor Science and Technology
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    • v.2 no.1
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    • pp.3-10
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    • 1993
  • Polycrystalline CdS thin films were grown on ceramic substrate using a chemical bath deposition method. They were annealed at various temperature and X-ray diffraction patterns were measured by X-ray diffractometer in order to study CdS polycrystal structure. Using extrapolation method of X-ray diffraction patterns for the CdS samples annealed in $N_{2}$ gas at $550^{\circ}C$ it was found hexagonal structure whose lattice constants $a_{o}$ and $c_{o}$ were $4.1364{\AA}$ and $6.7129{\AA}$, respectively. Its grain size was about $0.35{\mu}m$. Hall effect on this sample was measured by Van der Pauw method and studied on carrier density and mobility defending on temperature. From Hall data, the mobility was likely to be decreased by piezo electric scattering at temperature range of 33K and 150k and by polar optical scattering at temperature range of 150K and 293K. We measured also spectral response, sensitivity (${\gamma}$), maximum allowable power dissipation and response time on these samples.

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Characterization of CdSe Thin Film Using Chemical Bath Deposition Method (Chemical Bath Deposition 방법으로 제작한 CdSe 박막의 특성)

  • Hong, K.J.;Lee, S.Y.;You, S.H.;Suh, S.S.;Moon, J.D.;Shin, Y.J.;Jeong, T.S.;Shin, H.K.;Kim, T.S.;Song, J.H.;Rheu, K.S.
    • Journal of Sensor Science and Technology
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    • v.2 no.1
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    • pp.81-86
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    • 1993
  • Polycrystalline CdSe thin films were grown on ceramic substrate using a chemical bath deposition (CBD) method. They were annealed at various temperature and X-ray diffraction patterns were measured by X-ray diffractometer in order to study CdSe polycrystal structure. Using extrapolation method of X-ray diffraction patterns for the CdSe samples annealed in $N_{2}$ gas at $450^{\circ}C$ it was found hexagonal structure whose lattice parameters $a_{o}$ and $c_{o}$ were $4.302{\AA}$ and $7.014{\AA}$, respectively. Its grain size was about $0.3{\mu}m$. Hall effect on this sample was measured by Van der Pauw method and studied on carrier density and mobility depending on temperature. From Hall data, the mobility was likely to be decreased by piezo electric scattering at temperature range of 33 K and 200 K, and by polar optical scattering at temperature range of 200 K and 293 K. We measured also spectral response, sensitivity (${\gamma}$), maximum allowable power dissipation and response time on these samples.

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A Study on the Long-Term Variations of Annual Maximum Surge Heights at Sokcho and Mukho Harbors (속초와 묵호항의 연간 최대해일고의 장기간 변동성에 대한 고찰)

  • Kwon, Seok-Jae;Moon, Il-Ju;Lee, Eun-Il
    • Journal of Korean Society of Coastal and Ocean Engineers
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    • v.20 no.6
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    • pp.564-574
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    • 2008
  • This study investigates a long-term variation of annual maximum surge heights(AMSH) and main characteristics of high surge events, which is influenced by the global warming and intensifying typhoons, using sea level data at Sokcho and Mukho tidal stations over 34 years ($1974{\sim}2007$). It is found that the there is a longterm uptrend of the AMSH at Sokcho (8.3 cm/34yrs) and at Mukho (8.7 cm/34yrs), which is significant within 95% confidence level based on the linear regression. The statistical analysis reveals that 53% of the AMSH occurs during typhoon's event in both tidal stations and the highest surge records are mostly produced by the typhoon. It is concluded that the uptrend in the AMSH is attributed by the increasing typhoon activities globally as well as locally in Korea due to the increased sea surface temperature in tropical oceans. The continuous efforts monitering and predicting the extreme surge events in the future warm environments are required to prevent the growing storm surge damage by the intensified typhoon.

Estimation of Radio Frequency Electric Field Strength for Dielectric Heating of Phenol-Resorcinol-Formaldehyde Resin Used for Manufacturing Glulam (구조용 집성재 제조용 접착제(Phenol-Resorcinol-Formaldehyde Resin) 유전 가열을 위한 고주파 전기장 세기 추산)

  • Yang, Sang-Yun;Han, Yeonjung;Park, Yonggun;Eom, Chang-Deuk;Kim, Se-Jong;Kim, Kwang-Mo;Park, Moon-Jae;Yeo, Hwanmyeong
    • Journal of the Korean Wood Science and Technology
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    • v.42 no.3
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    • pp.339-345
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    • 2014
  • For enhancing productivity of glulam, high frequency (HF) curing technique was researched in this study. Heat energy is generated by electromagnetic energy dissipation when HF wave is applied to a dielectric material. Because both lamina and adhesives have dielectric property, internal heat generation would be occurred when HF wave is applied to glulam. Most room temperature setting adhesives such as phenol-resorcinol-formaldehyde (PRF) resin, which is popularly used for manufacturing glulam, can be cured more quickly as temperature of adhesives increases. In this study, dielectric properties of larch wood and PRF adhesives were experimentally evaluated, and the mechanism of HF heating, which induced the fast curing of glue layer in glulam, was theoretically analyzed. Result of our experiments showed relative loss factor of PRF resin, which leads temperature increase, was higher than that of larch wood. Also, it showed density and specific heat of PRF, which are resistance factors of temperature increase, were higher than those of wood. It was expected that the heat generation in PRF resin by HF heating would occur greater than in larch wood, because the ratio of relative loss factor to density and specific heat of PRF resin was greater than that of larch wood. Through theoretical approach with the experimental results, the relative strengths of ISM band HF electric fields to achieve a target heating rate were estimated.

Fabrication and Evaluation of Heat Transfer Property of 50 Watts Rated LED Array Module Using Chip-on-board Type Ceramic-metal Hybrid Substrate (Chip-on-board 형 세라믹-메탈 하이브리드 기판을 적용한 50와트급 LED 어레이 모듈의 제조 및 방열특성 평가)

  • Heo, Yu Jin;Kim, Hyo Tae
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.149-154
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    • 2018
  • This paper describes the fabrication and heat transfer property of 50 watts rated LED array module where multiple chips are mounted on chip-on-board type ceramic-metal hybrid substrate with high heat dissipation property for high power street and anti-explosive lighting system. The high heat transfer ceramic-metal hybrid substrate was fabricated by conformal coating of thick film glass-ceramic and silver pastes to form insulation and conductor layers, using thick film screen printing method on top of the high thermal conductivity aluminum alloy heat-spreading panel, then co-fired at $515^{\circ}C$. A comparative LED array module with the same configuration using epoxy resin based FR-4 PCB with thermalvia type was also fabricated, then the thermal properties were measured with multichannel temperature sensors and thermal resistance measuring system. As a result, the thermal resistance of the ceramic-metal hybrid substrate in the $4{\times}9$ type LEDs array module exhibited about one third to the value as that of FR-4 substrate, implying that at least triple performance of heat transfer property as that of FR-4 substrate was realized.

A Study of a Pilot Test for a Blasting Performance Evaluation Using a Dry Hole Charged with ANFO (건공화 공법의 발파 성능 평가를 위한 현장 시험에 관한 연구)

  • Lee, Seung Hun;Chong, Song-Hun;Choi, Hyung Bin
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.42 no.2
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    • pp.197-208
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    • 2022
  • The existence of shallow bedrock and the desire to use underground space necessitate the use of blasting methods. The standard blasting method under water after drilling is associated with certain technical difficulties, including reduced detonation power, the use of a fixed charge per delay, and decoupling. However, there is no blasting method to replace the existing blasting method. In this paper, a dry hole charged with ANFO blasting is assessed while employing a dry hole pumping system to remove water from the drill borehole. Additional standard blasting is also utilized to compare the blasting performances of the two methods. The least-squares linear regression method is adopted to analyze the blasting vibration velocity quantitatively using the measured vibration velocity for each blasting method and the vibration velocity model as a function of the scaled distance. The results show that the dry hole charged with ANFO blasting will lead to greater damping of the blasting vibration, more energy dissipation to crush the surrounding rock, and closer distances for the allowable velocity of the blasting vibration. Also, standard blasting shows much longer influencing distances and a wider range of the blasting pattern. The pilot test confirms the blasting efficiency of dry hole charged with ANFO blasting.

Numerical and experimental analysis of aerodynamics and aeroacoustics of high-speed train using compressible Large Eddy Simulation (압축성 대와류모사를 이용한 고속열차의 공력 및 공력소음의 수치적/실험적 분석)

  • Kwongi Lee;Cheolung Cheong;Jaehwan Kim;Minseung Jung
    • The Journal of the Acoustical Society of Korea
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    • v.43 no.1
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    • pp.95-102
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    • 2024
  • Due to technological advances, the cruising speed of high-speed trains is increasing, and aerodynamic noise generated from the flow outside the train has been an important consideration in the design stage. To accurately predict the flow-induced noise, high-resolution generation of sound sources in the near field and low-dissipation of sound propagation in the far field are required. This should be accompanied by a numerical grid and time resolution that can properly consider both temporal and spatial scales for each component of the real high-speed train. To overcome these challenges, this research simultaneously calculates the external flow and acoustic fields of five high-speed train cars of real-scale and at operational running speeds using a threedimensional unsteady Large Eddy Simulation technique. To verify the numerical analysis, the measurements of the wall pressure fluctuation and numerical results are compared. The Ffowcs Williams and Hawking equation is used to predict the acoustic power radiated from the high-speed train. This research is expected to contribute to noise reduction based on the analysis of the aerodynamic noise generation mechanism of high-speed trains.

A 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS ADC Based on High-Accuracy Integrated Capacitors (높은 정확도를 가진 집적 커페시터 기반의 10비트 250MS/s $1.8mm^2$ 85mW 0.13un CMOS A/D 변환기)

  • Sa, Doo-Hwan;Choi, Hee-Cheol;Kim, Young-Lok;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.58-68
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    • 2006
  • This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.