• 전기학회논문지P
• /
• 제58권2호
• /
• pp.207-213
• /
• 2009

Electrolytic capacitors have been widely used in power electronics system because of the features of large capacitance, small size, high-voltage, and low-cost. Electrolytic capacitors, which is most of the time affected by aging effect, plays a very important role for the power electronics system quality and reliability. Therefore it is important to estimate the parameter of an electrolytic capacitor to predict the failure. This paper proposed a novel fault diagnosis method of an electrolytic capacitor used for voltage smoothing in boost DC converter. The equivalent series resistance(ESR) of electrolytic capacitor estimated from FFT result of filtered waveform of capacitor voltage/current. Main advantage of the proposed method include circuit simplicity and easy implementation. Simulation and experimental results are shown to verify the performance of the proposed method.

• KIEE International Transactions on Electrophysics and Applications
• /
• 제2C권6호
• /
• pp.292-296
• /
• 2002

A new sustain driving method for the AC PDP is presented. In this driving method, the voltage source is connected to a storage capacitor, this storage capacitor charges an intermediate capacitor through LC resonance, and the panel is charged from the intermediate capacitor indirectly. In this way, the current flowing into the AC PDP when the sustain discharge occurs is reduced because the current is indirectly supplied from a capacitor, a limited source of charge. Thus, the input power to the output luminance efficiency is improved. Since the voltage supplied to the storage capacitor is doubled through LC resonance, this method call drive an AC PDP with a voltage source of about half of the voltage necessary in the conventional driving methods. The experiments showed that this charge-controlled driving method could drive ail AC PDP with a voltage source of as low as 107V. Using a panel of the conventional structure, luminous efficiency of 1.28 lm/W was achieved.

• Journal of Power Electronics
• /
• 제16권1호
• /
• pp.133-141
• /
• 2016

This paper focuses on the development of a Five-Level Flying-Capacitor Dual Buck Inverter (FLFCDBI) based on the main circuit of dual buck inverters. This topology has been described as not having any shoot-through problems, no body-diode reverse recovery problems and the half-cycle work mode found in the traditional Multi-Level Flying-Capacitor Inverter (MLFCI). It has been shown that the flying-capacitor voltages of this inverter can be regulated by the redundant state selection within one pole. The voltage balance of the flying-capacitors can be achieved by charging or discharging in the positive (negative) half cycles by choosing the proper logical algorithms. This system has a simple structure but demonstrates improved performance and reliability. The validity of this inverter is conformed through computer-aided simulation and experimental investigations.

• Journal of Power Electronics
• /
• 제18권6호
• /
• pp.1720-1728
• /
• 2018

This paper proposes a novel soft starting algorithm by using PWM inverter technique to control an amplitude of the motor starting current at a single-phase induction motor (SPIM). Traditional SPIM starting methods such as a Split-Phase, Capacitor-Start, Permanent-Split Capacitor (PSC), Capacitor-Start Capacitor-Run (CSCR), basically cannot control the magnitude of starting current due to the fixed system structures. Therefore, in this paper, a soft starting algorithm based on a proportional resonant (PR) control with a variable and constant frequency is proposed to reduce the inrush current and starting up time. In addition, a transition algorithm for operation modes is devised to generate a constant voltage and constant frequency (CVCF). The validity and effectiveness of the proposed soft starting method and transition algorithm are verified through experimental results.

• Journal of Power Electronics
• /
• 제9권3호
• /
• pp.386-395
• /
• 2009

In this paper, a new control algorithm for the dynamic voltage restorer (DVR) is proposed to regulate the load terminal voltage during various power quality problems that include sag, swell, harmonics and unbalance in the voltage at the point of common coupling (PCC). The proposed control strategy is an Adaline (Adaptive linear element) Artificial Neural Network (ANN) and is used to control a capacitor supported DVR for power quality improvement. A capacitor supported DVR does not need any active power during steady state because the voltage injected is in quadrature with the feeder current. The control of the DVR is implemented through derived reference load terminal voltages. The proposed control strategy is validated through extensive simulation studies using the MATLAB software with its Simulink and SimPower System (SPS) toolboxes. The DVR is found suitable to support its dc bus voltage through the control under various disturbances.

• Journal of Electrical Engineering and Technology
• /
• 제8권3호
• /
• pp.428-435
• /
• 2013

Flexible AC Transmission System (FACTS) application study on enhancing the flexibility of AC power system has continued to make progress. A thyristor-controlled series capacitor (TCSC) is a useful FACTS device that can control the power flow by adjusting line impedances and minimize the loss of power flow and voltage drop in a transmission system by adjusting line impedances. Reduced power flow loss leads to increased loadability, low system loss, and improved stability of the power system. This study proposes the optimal location and compensation rate method for TCSCs, by considering both the power system loss and voltage drop of transmission systems. The proposed method applies a multi-objective function consisting of a minimizing function for power flow loss and voltage drop. The effectiveness of the proposed method is demonstrated using IEEE 14- and a 30-bus system.

• 전자공학회논문지
• /
• 제53권10호
• /
• pp.123-130
• /
• 2016

고주파 유도가열장치는 LC 공진회로에 고주파 전원을 인가하여 금속을 가열 할 수 있다. 공진회로는 워크 코일과 전도 냉각 커패시터로 구성되며, 커패시터의 특성에 따라 열처리 설비의 성능을 좌우한다. 그러나 전도 냉각 커패시터는 국내 원천기술의 연구개발 부족으로 해외 수입 의존도가 높다. LC 공진 시 커패시터 내부의 발열을 최소화하고, 무효 전력손실을 줄이며, 내 전압특성이 우수한 커패시터가 요구된다. 국산화를 위하여, 선진 제조사의 완성품 커패시터의 주파수 응답 특성 분석에 대한 선행 연구가 필요하다. 주어진 로그-로그 특성 곡선의 임의 점에서 값을 읽기 위한 보간법을 연구하여 매틀랩 코딩으로 커패시터의 분석 도구로 적용하였다. 커패시터를 간단 화 된 RC 직렬 등가 회로로 가정하고, 등가 직렬 저항 ESL 값을 구하여 주파수 응답 특성 곡선을 재현하는 시뮬레이션을 시도하였다. 실제 무효전력의 피크 치에 대한 특성과 시뮬레이션 특성을 비교할 때 재현율이 83% 이상 결과 값으로 나타나는 것을 확인할 수 있었고, 이 알고리즘은 간단화 된 모델의 커패시터 특성곡선을 분석하여 예측 할 때 적용이 가능하다.

• 한국정보통신학회논문지
• /
• 제25권11호
• /
• pp.1627-1634
• /
• 2021

본 논문은 저전력 뉴럴 네트워크 가속기 SOC를 위한 아날로그 Convolution Filter용 저전력 초소형 ADC 회로 및 칩 설계 기술을 소개한다. 대부분의 딥러닝의 학습과 추론을 할 수 있는 Convolution neural network accelerator는 디지털회로로 구현되고 있다. 이들은 수많은 곱셈기 및 덧셈기를 병렬 구조로 구현하며, 기존의 복잡한 곱셉기와 덧셈기의 디지털 구현 방식은 높은 전력소모와 큰 면적을 요구하는 문제점을 가지고 있다. 이 한계점을 극복하고자 본 연구는 디지털 Convolution filter circuit을 Analog multiplier와 Accumulator, ADC로 구성된 Analog Convolution Filter로 대체한다. 본 논문에서는 최소의 칩면적와 전력소모로 Analog Accumulator의 아날로그 결과 신호를 디지털 Feature 데이터로 변환하는 8-bit SAR ADC를 제안한다. 제안하는 ADC는 Capacitor Array의 모든 Capacitor branch에 Split capacitor를 삽입하여 모든 branch의 Capacitor 크기가 균등하게 Unit capacitor가 되도록 설계하여 칩면적을 최소화 한다. 또한 초소형 unit capacitor의 Voltage-dependent capacitance variation 문제점을 제거하기 Flipped Dual-Capacitor 회로를 제안한다. 제안하는 ADC를 TSMC CMOS 65nm 공정을 이용하여 설계하였으며, 전체 chip size는 1355.7㎛², Power consumption은 2.6㎼, SNDR은 44.19dB, ENOB는 7.04bit의 성능을 달성하였다.

• Journal of Power Electronics
• /
• 제15권3호
• /
• pp.587-601
• /
• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• Journal of information and communication convergence engineering
• /
• 제15권1호
• /
• pp.62-71
• /
• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.