• Journal of IKEEE
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• v.26 no.1
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• pp.36-42
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• 2022

This study presents an analysis of the human body channel as an electric signal path using body impulse response (BIR). The human body communications (HBC) has recently emerged as an effective signal transmission method to create wireless body area networks (WBAN). We provide body channel characteristics based on measured BIR in a proper experimental environment for the HBC using capacitive coupling with a customized channel sounding device, which can be applied as a guideline for the HBC system design. The frequency response of the BIR, extracted by a customized signal processing for the measure signals, shows the channel path loss (CPS) between 0 MHz and 100 MHz with an average CPS of approximately 46.8 dB. In addition, the relative noise power distributions can provide estimations on the signal to noise ratio at the HBC receiver in terms of capacitor and resistor values in the measured frequency band and the frequency band lower than 3 MHz considering the baseband signal detection.

• Korean Journal of Materials Research
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• v.33 no.12
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• pp.517-524
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• 2023

BaTiO₃-Poly vinylidene fluoride (PVDF) solution was prepared by adding 0~25 wt% BaTiO₃ nanopowder and 10 wt% PVDF powder in solvent. BaTiO₃-PVDF film was fabricated by spreading the solution on a glass with a doctor blade. The output performance increased with increasing BaTiO₃ concentration. When the BaTiO₃ concentration was 20 wt%, the output voltage and current were 4.98 V and 1.03 ㎂ at an applied force of 100 N. However, they decreased when the over 20 wt% BaTiO₃ powder was added, due to the aggregation of particles. To enhance the output performance, the generator was poled with an electric field of 150~250 kV/cm at 100 ℃ for 12 h. The output performance increased with increasing electric field. The output voltage and current were 7.87 V and 2.5 ㎂ when poled with a 200 kV/cm electric field. This result seems likely to be caused by the c-axis alignment of the BaTiO₃ after poling treatment. XRD patterns of the poled BaTiO₃-PVDF films showed that the intensity of the (002) peak increased under high electric field. However, when the generator was poled with 250 kV/cm, the output performance of the generator degraded due to breakdown of the BaTiO₃-PVDF film. When the generator was matched with 800 Ω resistance, the power density of the generator reached 1.74 mW/m². The generator was able to charge a 10 ㎌ capacitor up to 1.11 V and turn on 10 red LEDs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of Sensor Science and Technology
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• v.9 no.3
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• pp.242-247
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• 2000

$Pb_{0.99}[(Zr_{0.6}Sn_{0.4})_{0.9}Ti_{0.1}]_{0.98}Nb_{0.02}O_3(PNZST)$ thin films were deposited by RF magnetron sputtering on $(La_{0.5}Sr_{0.5})CoO_3(LSCO)/Pt/Ti/SiO_2/Si$ substrate using a PNZST target with excess PbO of 10 mole%. The thin films deposited at substrate temperature of $500^{\circ}C$, and at RF power of 80W were crystallized to a perovskite phase after rapid thermal annealing(RTA). The thin films annealed at $650^{\circ}C$ for 10 seconds in air exhibited the good structures and electrical properties. The fabricated PNZST capacitor had a remanent polarization value of about $20\;{\mu}C/cm^2$ and coercive field of about 50 kV/cm. The reduction of the polarization after $2.2{\times}10^9$ switching cycles was less than 10%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Journal of the Korean Vacuum Society
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• v.17 no.4
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• pp.331-340
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• 2008

A method of measuring the current and voltage is suggested in the circuit of cold cathode fluorescent lamps (CCFLs) which are driven at a high frequency of $50{\sim}100\;kHz$ and a high voltage of several kV. It is difficult to measure the current and voltage in the lamp circuit, because the impedance of the probe at high voltage side causes the leakage current and the variation of luminance. According to the analysis of equivalence circuit with the probe impedance and leakage current, the proper measuring method is to adjust the input DC voltage and to keep the specific luminance when the probe is installed at a high voltage circuit. The lamp current is detected with a current probe or a high frequency current meter at the ground side and the voltage is measured with a high voltage probe at the high voltage side of lamp. The lamp voltage($V_C$) is measured between the ballast capacitor and the lamp electrode, and the output voltage($V_I$) of inverter is measured between inverter output and ballast capacitor. As the phases of lamp voltage($V_C$) and current ($I_G$) are nearly the same values, the real power of lamp is the product of the lamp voltage($V_C$) by the lamp current($I_G$). The measured value of the phase difference between inverter output voltage($V_I$) and lamp current($I_G$) is appreciably deviated from the calculated value at $cos{\theta}=V_C/V_I$.