• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.403-413
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• 2009

We compare three predistortion methods to prevent signal distortion and spectral re-growth due to the high PAPR (peak-to-average ratio) of OFDM signal and the non-linearity of high-power amplifiers. The three predistortion methods are pth order inverse, indirect learning architecture and look up table. The pth order inverse and indirect learning architecture methods requires less memory and has a fast convergence because these methods use a polynomial model that has a small number of coefficients. Nevertheless the convergence is fast due to the small number of coefficients and the simple computation that excludes manipulation of complex numbers by separate compensation for the magnitude and phase. The look up table method is easy to implement due to simple computation but has the disadvantage that large memory is required. Computer simulation result reveals that indirect learning architecture shows the best performance though the gain is less than 1 dB at $BER\;=\;10^{-4}$ for 64-QAM. The three predistorters are adaptive to the amplifier aging and environmental changes, and can be selected to the requirements for implementation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.4
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• pp.9-17
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• 2012

In this paper, we show the memory effect of the high-power amplifiers for wied-band signals, present a compensation method for the nonlinearity combined with memory effect, and analyze its performance. For the modeling and the compensation of the nonlinear high-power amplifier with memory effect, we investigate the Volterra series model, the Wiener model, and the Hammerstein model. As a compensator scheme, we propose a digital feedforward technique. Compared to analog feed-forward scheme, the proposed scheme has better stability and adaptability to the environmental changes. It has a simpler structure than the conventional digital nonlinear compensation schemes. The result of computer simulations using ADS of the Agilent shows that spectral re-growth is suppressed by more than 20 dB, which amounts to at least 10 dB back-off. Considering the compensation performance, implementation complexity, and convergence rate, we could conclude the Wiener model is most suitable for the proposed scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1143-1150
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• 2001

In this paper, we designed a downconverter for K-band satellite multipoint distribution service(SMDS). The designed downconverter consists of a low noise amplifiers, bandpass filter, stable local oscillator, drain mixer and If Amplifiers. Low noise amplifiers show 28㏈ gain and 1.5㏈ noise figure in the frequency range of 19.2㎓~20.2㎓, and a band pass filter has a -l㏈ insertion loss, and 18.25㎓ Stable local oscillator which is dielectric resonant oscillation, We obtained that the output power of the 18.25㎓ oscillation frequency is 0.5㏈m and the phase noise is the -84.67㏈c at 10KHz offset frequency. With the input RF signal the 19.2㎓~20.2㎓, conversion gain of the drain mixer shows 5㏈ at the Intermediate frequency range of 950MHz~1950MHz. We have proved that the designed downconverter satisfied the specification of a K-band satellite multipoint distribution service and it can be applied to the satellite internet receiver.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• ETRI Journal
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• v.31 no.5
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• pp.598-600
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• 2009

A highly efficient and compactly integrated balanced power amplifier (PA) for W-CDMA handset applications is presented. To overcome the size limit of a typical balanced PA, a bulky input divider is integrated into a PA MMIC, and a complex output network is replaced with simple lumped-element networks. For efficiency improvement at the low output power level, one of the two amplifiers in parallel is deactivated and the other is partially operated with corresponding load impedance optimization. The implemented PA shows excellent average current consumption of 34.5 mA in urban and 56.3 mA in suburban environments, while exhibiting very good load-insensitivity under condition of VSWR=4:1.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.401-406
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• 2004

In this paper, a new time-domain adaptive predistortion scheme is proposed to compensate for the nonlinearity of high power amplifiers (HPA) in OFDM systems. A complex Wiener-Hammerstein model (WHM) is adopted to describe the input-output relationship of unknown HPA with linear dynamics, and a power series model with memory (PSMWM) is used to approximate the HPA expressed by WHM. By using the PSMWM, the compensation input to HPA is calculated in a real-time manner so that the linearization from the predistorter input to the HPA output can be attained even if the nonlinear input-output relation of HPA is uncertain and changeable. In numerical example, the effectiveness of the proposed method is confirmed and compared with the identification method based on PSMWM.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.50-57
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• 1994

The analysis of the two-tone intermodulation distortion of multistage two-ports with gain and mismatching losses is presented with simplified two-port analyses and statistical viewpoint. The uncertainty obtained from unknown phase angles of the intermodulation distortion signals to the system designer is reduced using stochastic process, hence improving the accuracy of the solution. Based on the dc power dependance of third-order intercept point of each stage, the new efficient method for improving the total intercept point is also suggested with only the relation of dc power and available power gain criteria. Experimental verification on specific amplifiers used for cellular mobile communication comparing predicted and measured intercept points for various power conditions is presented.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.13-21
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• 1998

In this paper, we analyze the main-carrier cancellation characteristics of the nulling loop control circuit which is used for the main-carrier cancellation circuit of the feedforward linear power amplifier. A new nulling loop error control method is proposed to improve the linear power amplifier characteristics. With this analysis, the main carrier cancellation ratio can be estimated and the required specifications of the main and auxiliary amplifiers can be optimized for the economic and power efficiency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.53-61
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• 2014

In this paper, we present the design, fabrication and measurement of high efficiency GaN HEMT power amplifier using harmonic matching technique. In order to achieve high efficiency, harmonic load-pull simulation is performed, that is, the optimum load impedances are determined at $2^{nd}$ and $3^{rd}$ harmonic frequencies as well as at the fundamental. Then, the output matching circuit is designed based on harmonic load-pull simulation. The measurement of the fabricated power amplifier shows the linear gain of 20 dB and $P_{1dB}$(1 dB gain compression point) of 33.7 dBm at 1.85 GHz. The maximum power added efficiency(PAE) of 80.9 % is achieved at the output power of 38.6 dBm, which belongs to best efficiency performance among the reported high efficiency power amplifiers. For W-CDMA input signal, the power amplifier shows a PAE of 27.8 % at the average output power of 28.4 dBm, where an ACLR (Adjacent Channel Leakage Ratio) is measured to be -38.8 dBc. Digital predistortion using polynomial fitting was implemented to linearize the power amplifiers, which allowed about 6.2 dB improvement of an ACLR performance.