• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.1995-2003
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• 2014

Power semiconductor devices have been the major backbone for high-power electronic devices. One of important parameters in view of power semiconductor devices often characterize with a high breakdown voltage. Therefore, many efforts have been made, since the development of the Insulated Gate Bipolar Transistor (IGBT), toward having higher level of breakdown voltage, whereby the typical design thereof is focused on the structure using the field ring. In this study, in an attempt to make up more optimized field-ring structure, the characteristics of the field ring were investigated with the use of theoretical arithmetic model and methodologically the design of experiments (DOE). In addition, the IGBT having the field-ring structure was designed via simulation based on the finding from the above, the result of which was also analyzed. Lastly, the current study described the trench field-ring structure taking advantages of trench-etching process having the improved field-ring structure, not as simple as the conventional one. As a result of the simulation, it was found that the improved trench field-ring structure leads to more desirable voltage divider than relying on the conventional field-ring structure.

• Journal of Power Electronics
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• 제19권1호
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• pp.68-78
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• 2019

The emergence of high voltage conversion applications has resulted in a trend of using semiconductor device series associations. Series associations allow for operation at blocking voltages, which are higher than the nominal voltage for each of the semiconductor devices. The main challenge with these topologies is finding a way to guarantee the voltage balance between devices in both blocking and switching transients. Most of the methods that have been proposed to mitigate static and dynamic voltage unbalances result in increased losses within the device. This paper introduces a new series stack topology, where the voltage unbalances are reduced. This in turn, mitigates the switching losses. The proposed topology consists of a circuit that ensures the soft switching of each device, and one auxiliary circuit that allows for switching energy recovery. The principle for the topology operation is presented and experimental tests are performed for two modules. The topology performs excellently for switching transients on each of the devices. The voltage static unbalances were limited to 10%, while the activation/deactivation delay introduced by the lower module IGBT driver takes place in the dynamic unbalances. Thus, the switching losses are reduced by 40%, when compared to hard switching configurations.

• 마이크로전자및패키징학회지
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• 제21권2호
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• pp.13-21
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• 2014

Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.41-45
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• 2002

In modem manufacturing, new applations and technologies demand smaller, and functional devices to replace large systems. As miniaturization becomes a necessity, many companies are interested in small pumps for use in creating ultra-high vacuum, but past efforts to develop such systems have failed due to problems with vibration, stress, heat and power consumption. This paper shows analysis-based design techniques for high vacuum turbomolecular pump by finite element analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Journal of Electrical Engineering and Technology
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• 제11권5호
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• pp.1179-1189
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• 2016

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 춘계학술대회 논문집
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• pp.236-238
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• 1997

A cellular power amplifier using an APCVD(Atmospheric Pressure Chemical Vapor Deposition)-grown SiGe base HBT of ETRI has been designed with a linear simulation CAD. The Si/SiGe HBT with an emitter area of 2$\times$8${\mu}{\textrm}{m}$$^2$typically has a cutoff frequency(f$_{T}$) of 7.0 GHz and a maximum oscillation frequency(f$_{max}$) of 16.1 GHz with a pad de-embedding A packaged power Si/SiGe HBT with an emitter area of 2$\times$8$\times$80${\mu}{\textrm}{m}$$^2$typically shows a f$_{T}$ of 4.7 GHz and a f$_{max}$ of 7.1 GHz at a collector current (Ic) of 115 mA. The power amplifier exhibits a Forward transmission coefficient(S21) of 13.5 dB, an input and an output reflection coefficients of -42 dB and -45 dB respectively. Up to now the III-V compound semiconductor devices hale dominated microwave applications, however a rapid progress in Si-based technology make the advent of the Si/SiGe HBT which is promising in low to even higher microwave range because of lower cost and relatively higher reproducibility of a Si-based process.ess.ess.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.249-251
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• 2003

This paper discribes the analysis of the breakdown voltage characteristics of SOI LIGBT with dual epi-layer. In case of SOI LIGBT with dual epi-layer, if we used high doping concentration in epi-layer, we obtained higher breakdown voltage compared with typical device because of charge compensation effect, and we obtained low on-state resistivity characteristic in the same breakdown voltage. In this paper, we analyzed on-state and off-state characteristics of SOI LIGBT with dual epi-layer. Breakdown voltage of proposed LIGBT was shown 125V when $T_1=T_2=2.5{\mu}m$, $N_1=7{\times}10^{15}/cm^3$ and $N_2=3{\times}10^{15}/cm^3$, respectively Although we used high doping concentration and thin epi-layer thickness, breakdown voltage was increased compared with conventional devices.

• Journal of Semiconductor Engineering
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• 제1권1호
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.