• Title/Summary/Keyword: Power Semiconductor Devices

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Simulation based Comparative Loss Analysis and Output Characteristic for 25MW Class of High Power Multi-level Inverters (25MW급 대용량 멀티레벨 인버터의 시뮬레이션 기반 손실해석과 출력특성 비교 분석)

  • Kim, I-Gim;Park, Chan-Bae;Baek, Jei-Hoon;Kwak, Sang-Shin
    • The Transactions of the Korean Institute of Power Electronics
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    • v.20 no.4
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    • pp.337-343
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    • 2015
  • The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

Analysis of Lattice Temperature in Super Junction Trench Gate Power MOSFET as Changing Degree of Trench Etching

  • Lee, Byeong-Il;Geum, Jong Min;Jung, Eun Sik;Kang, Ey Goo;Kim, Yong-Tae;Sung, Man Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.263-267
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    • 2014
  • Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

Reducing Switching Losses in Indirect Matrix Converter Drives: Discontinuous PWM Method

  • Bak, Yeongsu;Lee, Kyo-Beum
    • Journal of Power Electronics
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    • v.18 no.5
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    • pp.1325-1335
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    • 2018
  • This paper presents a discontinuous pulse width modulation (DPWM) method to reduce switching losses in an indirect matrix converter (IMC) drive. The IMC has a number of power semiconductor switches. In other words, it consists of a rectifier stage and an inverter stage for AC/AC power conversion, which are composed of 12 and 6 switching devices, respectively. Therefore, the switching devices of the IMC suffer from high switching losses in the IMC drives. Various topologies to reduce switching losses have been studied by eliminating a number of switches from the rectifier stage. In this study, in contrast to prior research, a DPWM method is presented to reduce the switching losses of the inverter stage. The effectiveness of the proposed method to reduce switching losses in IMC drives is verified by simulations and experimental results.

Design and Characteristics of Modern Power MOSFETs for Integrated Circuits

  • Bang, Yeon-Seop
    • The Magazine of the IEIE
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    • v.37 no.8
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    • pp.50-59
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    • 2010
  • $0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

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Energy-efficient Real-time Computing by Utilizing Heterogenous Wireless Interfaces of the Smart Mobile Device in Small-IoT Environments (Small-IoT 환경에서 이기종 네트워크를 활용한 스마트 모바일 단말의 에너지 효율적 실시간 컴퓨팅 기법)

  • Lim, Sung-Hwa
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.3
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    • pp.108-112
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    • 2021
  • For smart mobile devices, the wireless communication module is one of the hardware modules that consume the most energy. If we can build a multi-channel multi-interface environment using heterogeneous communication modules and operate them dynamically, data transmission performance can be highly improved by increasing the parallelism. Also, because these heterogeneous modules have different data rates, transmission ranges, and power consumption, we can save energy by exploiting a power efficient and low speed wireless interface module to transmit/receive sporadic small data. In this paper, we propose a power efficient data transmission method using heterogeneous communication networks. We also compared the performance of our proposed scheme to a conventional scheme, and proved that our proposed scheme can save energy while guaranteeing reasonable data delivery time.

Comparative Analysis and Improvement of Transmitting Efficiency in RF Wireless Charging System (RF무선충전 시스템 전송효율 개선 및 비교 분석)

  • Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.4
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    • pp.102-107
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    • 2021
  • In this paper, the measurements of received power was shown and compared in two developed 5.8GHz 25W wireless charging systems. One is the system using commercial transmission antenna, and the other is the system using transmission antenna combined with metamaterial. The system combined with metamaterial shows higher received power due to negative reflective index of metamaterial. In addition, a comparative analysis of the systems shows that the transmission efficiency in the systems can decrease the real gain of transmission antenna due to higher side robe of beam pattern. The side robe beams of transmitting antenna interferes transmitted beam with the reflected beams from the bottom region due to the side robes. The failure problems of the RF wireless charging systems are discussed and proposed in order to charge mobile devices through the RF wireless charging system.

Applications of Plasma Modeling for Semiconductor Industry

  • Efremov, Alexandre
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.3-6
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    • 2002
  • Plasma processing plays a significant role in semiconductor devices technology. Development of new plasma systems, such as high-density plasma reactors, required development of plasma theory to understand a whole process mechanism and to be able to explain and to predict processing results. A most important task in this way is to establish interconnections between input process parameters (working gas, pressure, flow rate, input power density) and various plasma subsystems (electron gas, volume and heterogeneous gas chemistry, transport), which are closely connected one with other. It will allow select optimal ways for processes optimization.

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Measurement of Plasma Density Generated by a Semiconductor Bridge: Related Input Energy and Electrode Material

  • Kim, Jong-Dae;Jungling, K.C.
    • ETRI Journal
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    • v.17 no.2
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    • pp.11-19
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    • 1995
  • The plasma densities generated from a semiconductor bridge (SCB) device employing a capacitor discharge firing set have been measured by a novel diagnostic technique employing a microwave resonator probe. The spatial resolution of the probe is comparable to the separation between the two wires of the transmission lines (${\approx}$3 mm). This method is superior to Langmuir probes in this application because Langmuir probe measurements are affected by sheath effects, small bridge area, and unknown fraction of multiple ions. Measured electron densities are related to the land material and input energy. Although electron densities in the plasma generated by aluminum or tungsten-land SCB devices show a general tendency to increase steadily with power, at the higher energies, the electron densities generated from tungsten-land SCB devices are found to remain constant.

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Development Trends in Advanced Packaging Technology of Global Foundry Big Three (글로벌 파운드리 Big3의 첨단 패키징 기술개발 동향)

  • H.S. Chun;S.S. Choi;D.H. Min
    • Electronics and Telecommunications Trends
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    • v.39 no.3
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    • pp.98-106
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    • 2024
  • Advanced packaging is emerging as a core technology owing to the increasing demand for multifunctional and highly integrated semiconductors to achieve low power and high performance following digital transformation. It may allow to overcome current limitations of semiconductor process miniaturization and enables single packaging of individual devices. The introduction of advanced packaging facilitates the integration of various chips into one device, and it is emerging as a competitive edge in the industry with high added value, possibly replacing traditional packaging that focuses on electrical connections and the protection of semiconductor devices.

Performance Improvement of Asynchronous Mass Memory Module Using Error Correction Code (에러 보정 코드를 이용한 비동기용 대용량 메모리 모듈의 성능 향상)

  • Ahn, Jae Hyun;Yang, Oh;Yeon, Jun Sang
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.3
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    • pp.112-117
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    • 2020
  • NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.