• 제목/요약/키워드: Power Semiconductor

검색결과 1,990건 처리시간 0.024초

재난 상황에서 지상파 방송의 유용성 연구 (A Study on the Usibility of Terrestrial Broadcasting in Natural Disaster)

  • 이상운
    • 반도체디스플레이기술학회지
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    • 제17권3호
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    • pp.95-99
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    • 2018
  • In this study, take a look at natural disasters and technical characteristics such as frequency, bandwidth, transmission power, and service coverage of mobile communication and terrestrial broadcasting are compared as a means to provide disaster warning service in case of natural disaster, which is increasing in recent years. In the event of a disaster, mobile communication systems that take high frequency bands, low power transmission and narrow coverage can be disabled, but terrestrial broadcasting, which uses VHF and UHF with good frequency characteristics and high transmission power and wide service coverage provides stable services. As result terrestrial broadcast is useful as emergency warning or information in case of disaster.

초저전력 엣지 지능형반도체 기술 동향 (Trends in Ultra Low Power Intelligent Edge Semiconductor Technology)

  • 오광일;김성은;배영환;박성모;이재진;강성원
    • 전자통신동향분석
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    • 제33권6호
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    • pp.24-33
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    • 2018
  • In the age of IoT, in which everything is connected to a network, there have been increases in the amount of data traffic, latency, and the risk of personal privacy breaches that conventional cloud computing technology cannot cope with. The idea of edge computing has emerged as a solution to these issues, and furthermore, the concept of ultra-low power edge intelligent semiconductors in which the IoT device itself performs intelligent decisions and processes data has been established. The key elements of this function are an intelligent semiconductor based on artificial intelligence, connectivity for the efficient connection of neurons and synapses, and a large-scale spiking neural network simulation framework for the performance prediction of a neural network. This paper covers the current trends in ultra-low power edge intelligent semiconductors including issues regarding their technology and application.

Trench Gate 하단 P-영역을 갖는 IGBT의 전기적 특성에 관한 연구 (Study on Electric Characteristics of IGBT Having P Region Under Trench Gate)

  • 안병섭;육진경;강이구
    • 한국전기전자재료학회논문지
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    • 제32권5호
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    • pp.361-365
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    • 2019
  • Although there is no strict definition of a power semiconductor device, a general description is a semiconductor that has capability to control more than 1 W of electricity. Integrated gate bipolar transistors (IGBTs), which are power semiconductors, are widely used in voltage ranges above 300 V and are especially popular in high-efficiency, high-speed power systems. In this paper, the size of the gate was adjusted to test the variation in the yield voltage characteristics by measuring the electric field concentration under the trench gate. After the experiment Synopsys' TCAD was used to analyze the efficiency of threshold voltage, on-state voltage drop, and breakdown voltage by measuring the P- region and its size under the gate.

Small-IoT 환경에서 이기종 네트워크를 활용한 스마트 모바일 단말의 에너지 효율적 실시간 컴퓨팅 기법 (Energy-efficient Real-time Computing by Utilizing Heterogenous Wireless Interfaces of the Smart Mobile Device in Small-IoT Environments)

  • 임성화
    • 반도체디스플레이기술학회지
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    • 제20권3호
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    • pp.108-112
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    • 2021
  • For smart mobile devices, the wireless communication module is one of the hardware modules that consume the most energy. If we can build a multi-channel multi-interface environment using heterogeneous communication modules and operate them dynamically, data transmission performance can be highly improved by increasing the parallelism. Also, because these heterogeneous modules have different data rates, transmission ranges, and power consumption, we can save energy by exploiting a power efficient and low speed wireless interface module to transmit/receive sporadic small data. In this paper, we propose a power efficient data transmission method using heterogeneous communication networks. We also compared the performance of our proposed scheme to a conventional scheme, and proved that our proposed scheme can save energy while guaranteeing reasonable data delivery time.

RF무선충전 시스템 전송효율 개선 및 비교 분석 (Comparative Analysis and Improvement of Transmitting Efficiency in RF Wireless Charging System)

  • 손명식
    • 반도체디스플레이기술학회지
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    • 제20권4호
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    • pp.102-107
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    • 2021
  • In this paper, the measurements of received power was shown and compared in two developed 5.8GHz 25W wireless charging systems. One is the system using commercial transmission antenna, and the other is the system using transmission antenna combined with metamaterial. The system combined with metamaterial shows higher received power due to negative reflective index of metamaterial. In addition, a comparative analysis of the systems shows that the transmission efficiency in the systems can decrease the real gain of transmission antenna due to higher side robe of beam pattern. The side robe beams of transmitting antenna interferes transmitted beam with the reflected beams from the bottom region due to the side robes. The failure problems of the RF wireless charging systems are discussed and proposed in order to charge mobile devices through the RF wireless charging system.

토템폴 브리지리스 PFC에서 동기정류 스위치의 효율 영향에 관한 연구 (A Study on Influence of Synchronous Rectification Switch on Efficiency in Totem Pole Bridgeless PFC)

  • 유정상;안태영
    • 반도체디스플레이기술학회지
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    • 제20권4호
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    • pp.108-113
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    • 2021
  • In this paper, a totem pole PFC was structured in two methods with FET and diode for low-speed switch while GaN FET was used for high-speed switch. Internal power loss, power conversion efficiency and steady-state characteristics of the two methods were compared in the totem pole bridgeless PFC circuit which is widely applied in large-capacity and high-efficiency switching rectifier of 500W or more. In order to compare and confirm the steady-state characteristics under equal conditions, a 2kW class totem pole bridgeless PFC was constructed and the experimental results were analyzed. From the experimental results, it was confirmed that the low-speed switch operation has a large difference in efficiency due to the internal conduction loss of the low-speed switch at a low input voltage. Especially, input power factor and load characteristic showed no difference regardless of the low-speed switch operation.

반도체 테스트 비용 절감을 위한 랜덤 테스트 효율성 향상 기법 (A Method on Improving the Efficiency of Random Testing for VLSI Test Cost Reduction)

  • 이성제;이상석;안진호
    • 반도체디스플레이기술학회지
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    • 제22권1호
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    • pp.49-53
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    • 2023
  • In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

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PFC 스위칭 정류기에서 손실인자에 의한 내부손실과 효율분석에 관한 연구 (A Study on the Internal Loss and Efficiency Analysis by Loss Factors in PFC Switching Rectifier)

  • 안태영
    • 반도체디스플레이기술학회지
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    • 제23권2호
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    • pp.50-54
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    • 2024
  • In this paper, we propose a theoretical method to systematically analyze the power conversion efficiency of a single-phase PFC switching rectifier. Boost-type PFC was organized in order of highest correlation with load current using steady-state analysis results and introduced the concept of loss factor. The loss factors for each major element are summarized and presented in a table. This paper makes it easier to understand the internal loss and power conversion efficiency of the rectifier for loss factors. Lastly, to confirm the validity of the efficiency analysis results reflecting the loss factors, loss and efficiency analysis of the 2.5kW PFC rectifier was performed. The results were compared with data from a 2.5kW PFC circuit for evaluation. As a result, the usefulness of power conversion efficiency analysis reflecting the loss factors proposed in this paper was confirmed.

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4H-SiC와 산화막 계면에 대한 혼합된 일산화질소 가스를 이용한 산화 후속 열처리 효과 (Effect of High-Temperature Post-Oxidation Annealing in Diluted Nitric Oxide Gas on the SiO2/4H-SiC Interface)

  • 김인규;문정현
    • 한국전기전자재료학회논문지
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    • 제37권1호
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    • pp.101-105
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    • 2024
  • 4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (Ron,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (Dit) at the SiO2/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO2/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N2 diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N2 gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO2/4H-SiC interface, thereby reducing the Dit.

고전계 하에서 반도체 연면방전 특성 (The Characteristics of Surface Flashover on the Semiconductor in High Electric-Field)

  • 이세훈;이충식
    • 조명전기설비학회논문지
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    • 제16권1호
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    • pp.35-43
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    • 2002
  • 새로운 형태의 고체 상태의 대전력, 고속전자장치인 광전도 전력스위치(PCPS)의 개발과 대전력 및 고전압 상태하에서 광전도 전력스위치의 고전계 동작특성을 규명하기 위해서 많은 연구가 행해지고 있다. 그러나 표면 섬락 현상이 확실하고 효과 있는 고속, 고압스위칭 소자의 실현을 방해하고 있다. 이러한 연면방전의 물리적 현상의 명백한 이해는 새로운 기술과 소자구성을 발전시키는데 매우 중요할 뿐 아니라, 고전계·고전압에서의 동작특성을 향상시키는데 있어서도 특별한 의미를 가진다. 뿐만 아니라 고전계, 고전력 소자들을 안전하게 동작할 수 있게 하기 위해서도 필요하다. 연면방전 및 표면 절연파괴현상은 반도체 벌크 파괴 전계보다 훨씬 낮은 전계에서 적용되어 파괴된 모든 소자들에서 발생하기 때문에 이러한 문제를 해결하는 매우 실용적인 방법이 소자의 표면을 절연물로 페시베이션하는 것이다. 페시베이션된 소자들은 고전계에서 언페시페이션된 소자에 비해 매우 좋은 동작특성을 나타내므로, 본 논문에서는 페시베이션된 소자와 언페시베이션된 소자간의 I-E특성과 파괴 메커니즘을 규명하고 더 나아가 다중 페시베이션에 대한 몇몇 특성 값을 제시한다.