• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• 반도체디스플레이기술학회지
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• 제18권1호
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• pp.59-64
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• 2019

Recently, time synchronous has become important for satellite launch control facilities, multiple thermal power plants, and power system facilities. Information from time synchronous at each of these industrial sites requires time synchronization to control or monitor the system with correlation. In this paper, IRIG-B codes, which can be used for time synchronous, are used as specifications in IRIG standard 200-16. Signals from IRIG-B120 (Analog), IRIG-B000 (Digital), and one PPS are output from GPS receiver. Using the signal from IRIG-B120 (Analog), it passes through the signal from the analog amplifier and generates one PPS signal using the field-programmable gate array. The FPGA is used cyclone EPM570T100I5N. According to IEEE regulations, the error of one PPS is specified within 1us, but in this paper, the error is within 100ns. The output of the one PPS signal was then compared and tested against the one PPS signal on the GPS receiver to verify accuracy and reliability. In addition, the proposed time synchronous is simple to construct and structure, easy to implement, and provides high time precision compared to typical time synchronous. The output of the one PPS signals and IRIG-B000 signal will be used in many industry sectors.

• 반도체디스플레이기술학회지
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• 제13권4호
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• pp.59-63
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• 2014

Previous studies have selected wireless power transmission system using 2.45 GHz of ISM band, but the researches for 5.8 GHz microwave wireless power transmission have been relatively rare. The 5.8 GHz has some advantages compared with 2.45 GHz. Those are smaller antenna and smaller integrated system for RFIC. In this paper, the 5.8 GHz wireless power transmission system was developed and transmission efficiency was measured according to the distance. A transmitter sent the amplified microwaves through an antenna amplified by a power amplifier of 1W for 5.8 GHz, and a receiver was converted to DC from RF through a RF-DC Converter. In the 1W 5.8GHz wireless power transmission system, the converted currents and voltages were measured to evaluate transmission efficiency at each distance where LED lights up to 1m. The RF-DC Converter is designed and fabricated by impedance matching using full-wave rectifier circuit. The transmission-efficiency of the system shows from 1.05% at 0cm to 0.095% at 100cm by distance.

• 반도체디스플레이기술학회지
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• 제19권4호
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• pp.99-104
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• 2020

In this paper, efficiency and loss characteristics of GaN FET were reported by applying it into the QR flyback converter. In particular, for the comparison of efficiency characteristics, QR flyback converter experimental circuits with Si FET and with GaN FET were separately produced in 12W class. As a result of the experiment, the experimental circuit of the QR flyback converter using GaN FET reached a high efficiency of 90% or more when the load power was 2W or more, and the maximum efficiency was observed to be about 92%, and the maximum loss power was about 1.1W. Meanwhile, the efficiency of the experimental circuit with Si FET increased as the input voltage increased, and the maximum efficiency was observed to be about 82% when the load power was 9W or higher, and the maximum loss power was about 2.8W. From the results, it is estimated that that in the case of the experimental circuit applying the GaN FET switch, the power conversion efficiency was improved as the switching loss and conduction loss due to on-resistance were reduced, and the internal loss due to the synchronous rectifier was minimized. Consequently, it is concluded that the GaN FET is suitable for under 20W class power supply unit as a high efficiency power switch.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 반도체재료
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• pp.22-25
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• 2001

A thyristor switch circuit for capacitor discharge application, of which the equivalent circuit includes a resistor between cathode and gate of a reverse-conducting thyristor and an avalanche diode anti-parallel between its anode and gate to set thyristor tum-on voltage, is monolithically integrated by planar process with AVE double-implantation method. To ensure a lower breakdown voltage of the avalanche diode for thyristor tum-on than the break-over voltage of the thyristor, $p^+$ wells on thyristor p base layer are made by boron implantation/drive-in for a steeper doping profile with higher concentrations while rest p layers of thyristor and free-wheeling diode parts are formed with Al implantation/drive-in for a doping profile of lower steepness. The free-wheeling diode part is isolated from the thyristor part by formation of separated p-well emitter for suppressing commutation between them, which is achieved during the formation of thyristor p-base layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권1호
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• pp.21-26
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• 2003

4H-SiC Schottky rectifiers were exposed to pure Ar discharges in a planar coil Inductively Coupled Plasma system, as a function of source power, of chuck power and process pressure. The reverse breakdown voltage ($V_B$) decreased as a result of plasma exposure due to the creation of surface defects associated with the ion bombardment. The magnitude of the decrease was a function of both ion flux and ion energy. The forward turn-on voltage ($V_F$), on-state resistance ($R_{ON}$) and diode ideality factor (n) all increased after plasma exposure. The changes in all of the rectifier parameters were minimized at low power, high pressure plasma conditions.

• 마이크로전자및패키징학회지
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• 제27권2호
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• pp.53-58
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• 2020

전기자동차용 전력반도체 패키징 기술에 대한 분석을 수행하였다. 비정형 데이터인 특허들을 수집하여 유효특허를 도출하여 LDA 기법을 적용한 토픽모델링을 수행하였다. 20개의 토픽으로 분류하였고 각 토픽별 추출된 단어를 통해 기술에 대한 정의를 내렸다. 각 토픽의 대한 동향분석을 위해 연도별 빈도수에 대한 회귀분석을 통해 토픽별 Hot토픽과 Cold 토픽을 도출하여 전력반도체 패키징 기술의 동향을 분석하였다. Hot 토픽의 기술로는 내전압에 따른 패키지 구조 기술과 입출력 관련 제어 기술, 방열기술을 도출하였고 Cold 토픽 기술로는 인덕턴스 저감기술이 도출되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권5호
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• pp.290-294
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• 2003

Using a backpropagation neural network (BPNN), a high power semiconductor device was empirically modeled. The device modeled is a n-LDMOSFET and its electrical characteristics were measured with a HP4156A and a Tektronix curve tracer 370A. The drain-source current $(I_{DS})$ was measured over the drain-source voltage $(V_{DS})$ ranging between 1 V to 200 V at each gate-source voltage $(V_{GS}).$ For each $V_{GS},$ the BPNN was trained with 100 training data, and the trained model was tested with another 100 test data not pertaining to the training data. The prediction accuracy of each $V_{GS}$ model was optimized as a function of training factors, including training tolerance, number of hidden neurons, initial weight distribution, and two gradients of activation functions. Predictions from optimized models were highly consistent with actual measurements.

• 전력전자학회논문지
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• 제15권4호
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• pp.274-281
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• 2010

본 논문에서는 반도체 플라즈마 식각 시스템의 균일도 향상을 위한 CCP와 ICP 결합 임피던스정합 장치를 제안한다. 이중주파수 전원공급 장치는 CCP와 ICP로 구성되어 있고 첫 번째 구성은 고집적화를 위해 페라이트 코어를 사용한 유도 결합 플라즈마(ICP : Inductively Coupled Plasma)방식이며, 두 번째 구성은 셀 전체의 균일도 향상을 위한 용량 결합 플라즈마(CCP : Capacitively Coupled Plasma)방식이다. 제안된 시스템은 반도체 장비 산업에서 요구되는 높은 생산성을 실현할 수 있다. 본 논문에서는 제안된 시스템의 타당성을 검증하기 위해 CCP와 ICP 결합 임피던스정합 장치를 제작하였고, 이론적 분석과 27.12MHz 와 400kHz의 조건에서 시뮬레이션 및 실험을 진행하였다