• Title/Summary/Keyword: Power Semiconductor

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A Study on Electrical Characteristic Improvement & Design Parameters of Power MOSFET with Single Floating Island Structure (단일 Floating Island 구조 Power MOSFET의 전기적 특성 향상과 설계 파라미터에 관한 연구)

  • Cho, Yu Seup;Sung, Man Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.28 no.4
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    • pp.222-228
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    • 2015
  • Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device, it is essential to increase its conductance. However, a trade-off relationship between the breakdown voltage and conductance of the device have been the critical difficulty to improve. In this paper, theoretical analysis of electrical benefits on single floating island power MOSFET is proposed. By the method, the optimization point has set defining the doping limit under single floating island structure. The numerical multiple 2.22 was obtained which indicates the doping limit of the original device, improving its ON state voltage drop by 45%.

Gain Characteristics of Fabry-Perot Type AlGaAs Semiconductor Laser Amplifier (Fabry-Perot 공진기형 AlGaAs 반도체 레이저 증폭기의 이득특성)

  • 김도훈;권진혁
    • Korean Journal of Optics and Photonics
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    • v.2 no.2
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    • pp.67-73
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    • 1991
  • The unsaturated signal gain, signal gain bandwidth, and saturation power which are important parameters determining characteristics of the semiconductor laser amplifier were measured for an AlGaAs Fabry-Perot cavity type laser amplifier and compared with the results of Fabry-Perot formula. The unsaturated signal gain 25 dB is obtained near oscillation thereshold current at $0.7\mu\textrmW$ input power. The corresponding signal gain bandwidth was about 3 GHz. Also. We measured the variation of the saturation signal gain and saturation power.

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A Study on the Simulation of AlGaN/GaN HEMT Power Devices (AlGaN/GaN HEMT 전력소자 시뮬레이션에 관한 연구)

  • Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.4
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    • pp.55-58
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    • 2014
  • The next-generation AlGaN/GaN HEMT power devices need higher power at higher frequencies. To know the device characteristics, the simulation of those devices are made. This paper presents a simulation study on the DC and RF characteristics of AlGaN/GaN HEMT power devices. According to the reduction of gate length from $2.0{\mu}m$ to $0.1{\mu}m$, the simulation results show that the drain current at zero gate voltage increases, the gate capacitance decreases, and the maximum transconductance increases, and thus the cutoff frequency and the maximum oscillation frequency increase. The maximum oscillation frequency maintains higher than the cutoff frequency, which means that the devices are useful for power devices at very high frequencies.

The Switching Characteristics of Series-Connected Power Transistors (전력용 트랜지스터의 직렬연결시 스윗칭 특성)

  • 서범석;이택기;현동석
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.41 no.6
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    • pp.600-606
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    • 1992
  • The series connection of power switching semiconductor elements is essential when a high voltage converter is made, so researches are being conducted to further develop this technology. In the series connection of power switching semiconductor elements, the main problem is that simultaneous conduction at turn-on and simultaneous blocking at turn-off together with voltage balancing are unattainable because of the difference of their switching characteristics. In this paper a novel series connection algorithm is proposed, which can implement not only the synchronization of the points of turn-on and turn-off time but the dynamic voltage balancing in spite of the difference of each switching characteristics. The proposed method is that the compensated control signal is attained from the voltage feedback signal and applied to the series-connected power transistors independently. Computer simulation and experimental results verify its validity.

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A Study on Output Voltage Stabilization of 20W Class Multi-output QR Flyback Converter for Auxiliary Power (20W급 보조전원용 다출력 QR 플라이백 컨버터의 출력전압 안정화에 관한 연구)

  • Yoo, Jeong Sang;Gil, Yong Man;Kim, Hyun Bae;Ahn, Tae Young
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.3
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    • pp.157-160
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    • 2021
  • In this paper, a 20W class multi-output QR flyback converter for auxiliary power supply was designed to stabilize 4 output voltages, and the efficiency and load characteristics were compared and analyzed. It was checked if each output affects other output characteristics through experiment. As a result, the experimental circuit reached a high efficiency of 82.5% or more at a load power of over 20W, and the maximum power loss was 2.6W. Consequently, it was confirmed that all of 4 output voltages of the multi-output QR flyback converter constructed in this paper were stabilized within 0.5% in full-load range, and each output was independently controlled in an electrically isolated state.

An Analysis of Voltage Multiplier Circuits for Smart Phone RF Wireless Charging (스마트폰 RF 무선충전을 위한 전압 체배기 회로 분석)

  • Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.2
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    • pp.29-33
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    • 2021
  • A 5.8-GHz 1W wireless power transmission system was used for charging a smart phone. The voltage of one RF power receiver with antenna was not enough for charging. Several power receivers for charging a smart phone was connected serially. The voltage of several RF power receivers are highly enough for charging a smart phone within 50cm. However, the lack of current from small capacitances of RF-DC converters is not suitable for charging smart phone. It means very long charging time. In this paper, the voltage multiplier circuits for RF-DC converters were analyzed to increase the current and voltage at the same time to reduce the charging time in smartphone RF wireless charging. Through the analysis of multiplier circuits, the 7-stage parallel multiplier circuit with voltage-doubler units are suitable for charging the smartphone, which supplies 5V and 700mA at 3V@5.8GHz.

MRAM Technology for High Density Memory Application

  • Kim, Chang-Shuk;Jang, In-Woo;Lee, Kye-Nam;Lee, Seaung-Suk;Park, Sung-Hyung;Park, Gun-Sook;Ban, Geun-Do;Park, Young-Jin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.185-196
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    • 2002
  • MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

A Study on Temperature Dependent Super-junction Power TMOSFET

  • Lho, Young Hwan
    • Journal of IKEEE
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    • v.20 no.2
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    • pp.163-166
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    • 2016
  • It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

  • Lee, Myoung-Sun;Joe, Sung-Min;Yun, Jang-Gn;Shin, Hyung-Cheol;Park, Byung-Gook;Park, Sang-Sik;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.3
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    • pp.360-369
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    • 2012
  • The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

Nanoscale Characterization of a Heterostructure Interface Properties for High-Energy All-Solid-State Electrolytes (고에너지 전고체 전해질을 위한 나노스케일 이종구조 계면 특성)

  • Sung Won Hwang
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.1
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    • pp.28-32
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    • 2023
  • Recently, the use of stable lithium nanostructures as substrates and electrodes for secondary batteries can be a fundamental alternative to the development of next-generation system semiconductor devices. However, lithium structures pose safety concerns by severely limiting battery life due to the growth of Li dendrites during rapid charge/discharge cycles. Also, enabling long cyclability of high-voltage oxide cathodes is a persistent challenge for all-solid-state batteries, largely because of their poor interfacial stabilities against oxide solid electrolytes. For the development of next-generation system semiconductor devices, solid electrolyte nanostructures, which are used in high-density micro-energy storage devices and avoid the instability of liquid electrolytes, can be promising alternatives for next-generation batteries. Nevertheless, poor lithium ion conductivity and structural defects at room temperature have been pointed out as limitations. In this study, a low-dimensional Graphene Oxide (GO) structure was applied to demonstrate stable operation characteristics based on Li+ ion conductivity and excellent electrochemical performance. The low-dimensional structure of GO-based solid electrolytes can provide an important strategy for stable scalable solid-state power system semiconductor applications at room temperature. The device using uncoated bare NCA delivers a low capacity of 89 mA h g-1, while the cell using GO-coated NCA delivers a high capacity of 158 mA h g−1 and a low polarization. A full Li GO-based device was fabricated to demonstrate the practicality of the modified Li structure using the Li-GO heterointerface. This study promises that the lowdimensional structure of Li-GO can be an effective approach for the stabilization of solid-state power system semiconductor architectures.

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