• Journal of Power Electronics
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• v.16 no.4
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• pp.1426-1437
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• 2016

In different industrial and mission oriented applications, redundant or standby semiconductor systems can be implemented to improve the reliability of power electronics equipment. The proper structure for implementation can be one of the redundant or standby structures for series or parallel switches. This selection is determined according to the type and failure rate of the fault. In this paper, the reliability and the mean time to failure (MTTF) for each of the series and parallel configurations in two redundant and standby structures of semiconductor switches have been studied based on different failure rates. The Markov model is used for reliability and MTTF equation acquisitions. According to the different values for the reliability of the series and parallel structures during SC and OC faults, a comprehensive comparison between each of the series and parallel structures for different failure rates will be made. According to the type of fault and the structure of the switches, the reliability of the switches in the redundant structure is higher than that in the other structures. Furthermore, the performance of the proposed series and parallel structures of switches during SC and OC faults, results in an improvement in the reliability of the boost dc/dc converter. These studies aid in choosing a configuration to improve the reliability of power electronics equipment depending on the specifications of the implemented devices.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.149-153
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• 2019

The technology of electronic packaging among semiconductor technologies is evolving as an axis of the market in its own field beyond the simple assembly process of the past. In the field of electronic packaging technology, the packaging of power modules plays an important role for green electric vehicles. In this power module packaging, the thermal reliability is an important factor, and silicon nitride plays an important part of package substrates, Silicon nitride is a compound that is not found in nature and is made by chemical reaction between silicon and nitrogen. In this study, this core material, silicon nitride, was fabricated by reaction bonded silicon nitride. The fabricated silicon nitride was studied for thermo-mechanical properties, and through this, the structure of power module packaging was made using reaction bonded silicon nitride. And the characteristics of stress were evaluated using finite element analysis conditions. Through this, it was confirmed that reaction bonded silicon nitride could replace the silicon nitride as a package substrate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.575-580
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• 2010

This paper is to design an optimum power conversion device for the system required for development of a low cost 3-phase power inverter. For this purpose, in order to meet with endurance required by the industry, failure mode is standardized to guarantee lifetime of a power semiconductor by monitoring real time power loss and to facilitate failure mode analysis. As normality of heat loss of a power semiconductor is identified remaining in a certain range by comparing heat rise slope between that is calculated by using average current or average loss and that is measured at a heat sink, its feasibility is confirmed by experiment.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.21-24
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• 2019

In this paper, 5.8GHz 25W microwave wireless power transmission system was developed. The transmission system is composed of a signal generator, a 1W drive amplifier, a 25W power amplifier, and a circularly polarized transmission antenna. The receiving system was fabricated with an integrated receiver that combines a circularly polarized receiving antenna, a pass band filter, and an RF-DC converter. And a multi-integrated receiver had twelve parts, including an integrated receiver. Under the conditions, voltage and current were measured for the system at 5cm intervals from a minimum distance of 5cm to a maximum distance of 80cm. The power was calculated for the system. The results of the system are shown in tables and graphs. The power decreases with distance, but the power does not drop sharply due to a multi-integrated receiver.

• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.39-47
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• 2023

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

• Journal of Advanced Engineering and Technology
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• v.10 no.2
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• pp.203-208
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• 2017

Due to global climate change issues, there is a growing demand for systems throughout the industry. In the case of power conversion, studies have been actively conducted to change the structure of the power conversion circuit and to apply new power devices. In particular, the WBG (Wide Band Gap), which is newly emerged device in the market for developing semiconductor technology, has demonstrated advantages in applying for various aspects in comparison to the existing Si (Silicon) Semiconductor. Recent research centers in the railway industry are focusing on developing technologies suitable for railway vehicles by utilizing these new developments in railway countries such as Japan and Europe. This paper researches the WBG device that is applicable to the auxiliary power supplies (APS) in railway system, and analyzes the downsizing effects to APS in high-speed railway by conducting a theoretical analysis and simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.1 no.1
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• pp.1-6
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• 1996

Recent trends of the power electronic industry in China have been summarized in this paper. Based on the applications of the power electronic products in the chinese industries the production trends of power semiconductor devices, drives, power supplies, power electronic industry used in power systems in China have been briefly reviewed.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.59-60
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• 2013

슈퍼캐패시터(Super Capacitor) 또는 울트라 캐패시터(Ultra Capacitor) 등으로 불리우는 전기 이중층 캐패시터(EDLC, Electric Double Layer Capacitor)는 기존 콘덴서보다 월등한 용량 특성을 가지며, 전극과 전해질의 화학반응을 이용하던 이차전지들과 달리 주로 계면반응을 사용한 축전원리를 이용하여 높은 출력밀도와 충방전 효율, 무제한에 가까운 사이클 특성을 가지고 있다. 또한 전류변화에 안정적이어서 기존의 이차전지와는 달리 보호회로를 생략할 수 있기 때문에 단순한 회로 구성이 가능하고 전극활물질로서 탄소재를 사용하여 환경 친화적인 특성을 가진 차세대 에너지저장장치라고 할 수 있다. 특히 50만 사이클이라는 우수한 수명특성으로 인해 기존의 이차전지가 사용되기 어려운 다양한 분야에 적용이 늘어가고 있는 추세에 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.278-283
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• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.