• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1827-1834
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• 2013

The existing PC-based desktop environment is being changed to a server-based virtual desktop environment due to various advantages such as security, mobility, and upgrade cost reduction. In this paper, a virtual computing lab service system which is applicable to the existing computer lab is designed and implemented using both an open source-based cloud computing platform and hypervisor. In addition, a node power scheduler is proposed in order to reduce power consumption in a server farm. The experimental results show that the power scheduler reduces power consumption considerably over the server farm without the power scheduler.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.222-229
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• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.36-44
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• 2010

When multi-user MIMO (Multiple-Input Multiple-Output) systems utilize a sum-rate maximization (SRM) scheduler, the throughput of the systems can be enhanced. However, fairness problems may arise because users located near cell edge or experiencing poor channel conditions are less likely to be selected by the SRM scheduler. In this paper, a weighted sum-rate maximization (WSRM) scheduler is used to enhance the fairness performance of the MIMO systems. Closed-form expressions for the optimal transmit power allocation of WSRM and corresponding weighted sum-rate (WSR) are derived in the 6-sector collaborative transmission system. Using the derived results, we propose an algorithm which searches the optimal power allocation for WSRM in the 3-sector collaborative transmission system. Based on the derived closed-form expressions and the proposed algorithm, we perform computer simulations to compare performance of the WSRM scheduler and the SRM scheduler with respect to the sum-rate and the log-sum-of-average rates. We further verify that the WSRM scheduler efficiently improves fairness performance by showing the enhanced performance of average transmission rates in low percentile region.

• International Journal of Control, Automation, and Systems
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• v.3 no.3
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• pp.493-501
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• 2005

A power plant simulation tool ('PowerSim') has been developed with 10 years experience from the development of a plant simulator for efficient modeling of a power plant. PowerSim is the first developed tool in Korea for plant simulation with various plant component models, instructor station function and the Graphic Model Builder (GMB). PowerSim is composed of a graphic editor using general purpose design software, a netlist converter, component models, the scheduler, Instructor Station and an executive. The graphic editor generates a netlist that shows the connection status of the various plant components from the Simdiagram, which is drawn by Icon Drag method supported by GUI environment of the PowerSim. Netlist Converter normalizes the connection status of the components. Scheduler makes scheduling for the execution of the device models according to the netlist. Therefore, the user makes Simdiagram based on the plant Pipe and Instrument Drawing (P&ID) and inputs the plant data for automatic simulating execution. This paper introduces Graphic Model Builder (GMB), instructor station, executive and the detailed introduction of thermal-hydraulic modeling. This paper will also introduce basic ideas on how the simulation Diagram, based on netlist generated from general purpose design software, is made and how the system is organized. The developed tool has been verified through the simulation of a real power plant.

• Journal of IKEEE
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• v.25 no.3
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• pp.479-484
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• 2021

This paper proposed and designed a structure to achieve high performance with a small number of cores in GPGPU with SIMT structure. GPGPU for application to mobile devices requires a structure to increase performance compared to power consumption. In order to reduce power consumption, the number of cores decreased, but to improve performance, the size of the warp scheduler for managing threads was set to 4, which was greatly reduced than 32 of general GPGPU. Reducing warp size can reduce the number of idle cycles in pipelines and efficiently apply memory latency to reduce miss penalty when accessing cache memory. The designed GPGPU measured computational performance using a test program that includes floating point operations and measured power consumption through a 28nm CMOS process to obtain 104.5GFlops/Watt as a performance per power. The results of this paper showed about four times better performance per power compared to Tegra K1 of Nvidia

• Journal of the Korea Society of Computer and Information
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• v.20 no.10
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• pp.91-97
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• 2015

In this paper, we propose a MCFQ I/O scheduler that is implemented by modifying the existing Linux CFQ I/O scheduler. MCFQ observes whether the user requested I/O bandwidth weight is well distributed. Based on the I/O bandwidth observation, we improved I/O performance of the existing bandwidth distribution ability by dynamically controlling the I/O time-slice of the virtual machine. The use of SSDs as storage has been increasing dramatically in recent computer systems due to their fast performance and low power usage. As the usage of SSD increases and prices fall, virtualized system administrators can take advantage of SSDs. However, studies on guaranteeing SLA(Service Level Agreement) services when multiple virtual machines share the SSD is still incomplete. In this paper was conducted to improve performance of the bandwidth distribution when multiple virtual machine are sharing a single SSD storage in a virtualized environment. In particular, it was observed that the performance of the bandwidth distribution varied widely when garbage collection occurs in the SSD. In order to reduce performance variance, we add a MoTS(Manager of Time Slice) on existing CFQ I/O scheduler.

• Journal of Advanced Navigation Technology
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• v.7 no.1
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• pp.59-71
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• 2003

The channel scheduler is suggested the radio resource management method in order to provide service with guaranteeing fairness and throughput to the users who use limited wireless channel. Proportional fairness scheduling algorithm is the channel scheduler used in the AMC(Adaptive Modulation and Coding)/TDM system, and this algorithm increases the throughput considering the user's time fairness. In this paper is suggested the channel scheduler combining CDM scheme available in AMC/TDM/CDM system. Unlike the system which only uses TDM which provide the only one user at the same slot, this scheduler can service a lot of users since this uses the CDM scheme with multi-cord channel. At every moment, allocation of transmission power to multi-channel users is problematic because of CDM scheme. In this paper, we propose a water-filling scheduling algorithm to solve the problem. Water-filling fairness(WF2) scheduling algorithm watches the average channel environment. So, this modified method guarantees fairness for each user in terms of power and service time.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.100-103
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• 1999

In this paper, a method for the efficient implementation of the PICNET network configurator for a distributed control system(DCS) is proposed. The network configurator is composed of the time parameter estimator and the period scheduler, the file generator. The main role of network configurator estimates time parameter, the pre-run time scheduling of the user input and make the period transmission table for operating the PICNET based distributed control system.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.11
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• pp.379-384
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• 2016

NAND flash storage is widely used for computer systems, because of it has faster response time, lower power consumption, and larger capacity per unit area than hard disk. However, currently used I/O scheduler in the operating system is optimized for characteristics of the hard disk. Therefore, the conventional I/O scheduler includes the unnecessary overhead in the case of the NAND flash storage to be applied. Particularly, when the write requests performed intensively, garbage collection is performed intensively. So, it occurs the problem that the processing of the I/O request delay. In this paper, we propose the new I/O scheduler to solve the problem of garbage collection performs intensively, and to optimize for NAND flash storage. In the result of performance evaluation, proposed scheme shows an improvement the user responsiveness by reducing 1% of the average read response time and 78% of the maximum response time.