• Journal of Electrical Engineering and Technology
• /
• v.12 no.4
• /
• pp.1593-1599
• /
• 2017

This paper presents a multi-channel light-emitting diode (LED) driver IC with a current-mode current regulator. The proposed current regulator replaces resistors for current sensing with a sequentially controlled single current sensor and a single regulation loop for sensing and regulating all LED channel currents. This minimizes the current mismatch among the LED channels and increases voltage headroom or, equivalently, power efficiency. The proposed LED driver IC was fabricated in a $0.35-{\mu}m$ BCD 60-V high voltage process, and the chip area is $1.06mm^2$. The measured maximum power efficiency is 93.4 % from a 12-V input, and the inter-channel current error is smaller than as low as ${\pm}1.3%$ in overall operating region.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.2
• /
• pp.193-201
• /
• 1998

In this paper, the standard Dole, Glover, Khargoneker, and Francis (abbr. : DGKF 1989) H\ulcorner controller (H\ulcornerC) is extended to the nonlinear feedback linearization-H\ulcorner/sliding mode controller (NFL-H\ulcorner/SMC), to tackle the problem of the unmeasurable state variables as in the conventional SMC, to obtain smooth control as the linearized controller in a linear system, and to improve the time-domain performance under a worst scenario. The proposed controller is obtained by combining the H\ulcorner estimator with the nonlinear feedback linearization-sliding mode controller (NFL-SMC) and it does not need to measure all the state variables as in the traditional SMC. The proposed controller is applied as a nonlinear power system stabilizer (PSS) for the improvement of the power system damping characteristics of an single machine infinite bus system (SMIBS) connected through a double circuit line. The effectiveness of the proposed controller is verified by nonlinear time-domain simulation in case of a 3-cycle line-to-ground fault and in case of the parameter variations for the AVR gain K\ulcorner and for the inertia moment M.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07b
• /
• pp.638-641
• /
• 2002

This paper presents design and construct of flat type step-down piezoelectric transformer for the application to AC-adapters. This piezoelectric transformer operated in resonance vibration mode. In this paper, Finite element method(FEM) was used for analysis piezoelectric transformers. Vibration mode and electric field of piezoelectric transformer at resonance frequency were simulated. Using this simulation, we manufactured flat type piezoelecric transformer and measured its output characteristics. As results, output power was linearly increased by increasing input power at resonance frequency. And it was found that the transformer exhibited an output power of 11.4[W] at 60[V] input voltage. From these results, we expect that this piezoelecric transformer can be applied to AC adapters.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.875-878
• /
• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2000.06a
• /
• pp.679-686
• /
• 2000

Reactor Noise is defined as the fluctuations of measured instrumentation signals during full-power operation of reactor which have informations on reactor system dynamics such as neutron kinetics, thermal-hydraulics, and structural dynamics. Reactor noise analyses of ex-core neutron detector signals have been performed to monitor the vibration modes of reactor internals such as fuel assembly and Core Support Barrel in Yonggwang 3&4 Nuclear Power Plant. A real time mode separation technique have been developed and applied for the analyses. It has been found that the first vibration mode frequency of the fuel assembly was around 2.5 Hz, the beam and shell mode frequencies of CSB(Core Support Barrel) 8 Hz and 14.5 Hz, respectively. Also the analyses data base have been constructed for the continuous monitoring and diagnose of the reactor internals.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.21 no.4
• /
• pp.374-383
• /
• 2011

A numerical model based on a mode method coupling beams and a rectangular plate is proposed to estimate radiation characteristics of an edge-clamped rectangular plate. The radiation efficiency and radiation power in the audio frequency range including the critical frequency can be predicted. The proposed model is rather simple and straightforward and gives reliable results comparing to the previous studies. The estimated radiation characteristics are compared to those of the pinned condition plates and also to those based on the formulae proposed by Maidanik. The radiation efficiency of the clamped plate seems a little higher than that of the pinned plate in the frequency range of corner and edge modes. It is explicitly shown that the power as well as efficiency at high frequencies is not influenced by these edge boundary conditions.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.1
• /
• pp.199-202
• /
• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Proceedings of the KIEE Conference
• /
• 2015.07a
• /
• pp.1058-1059
• /
• 2015

This paper describes a low-voltage ride-through method for the permanent magnet synchronous generator (PMSG) wind turbine system at a grid fault. The generator side converter regulates the DC link voltage instead of the grid side converter by storing the surplus active power in the rotor inertia during grid fault by the sliding mode controller. The grid side converter controls the grid active power keeping a maximum power point tracking. Simulation results for small scale PMSG wind turbine verify the efficiency of the control method.

• Journal of Power Electronics
• /
• v.11 no.4
• /
• pp.520-526
• /
• 2011

This paper presents a balanced soft-chopping circuit and a modified PI controller for a high speed 4/2 Switched Reluctance Motor (SRM) with a 16 pulse per revolution encoder. The proposed balanced soft-chopping circuit can supply double the switching frequency in the fixed switching frequency of power devices to reduce current ripple. The modified PI controller uses maximum voltage, back-emf voltage and PI control modes to overcome the over-shoot current due to the time delay effect of current sensing. The maximum voltage mode can supply a fast excitation current with consideration of the hardware time delay. Then the back-emf voltage mode can suppress the current over-shoot with consideration of the feedback signal delay. Finally, the PI control mode can adjust the phase current to a desired value with a fast switching frequency due to the proposed balanced soft-chopping technology.

• Proceedings of the KIEE Conference
• /
• 1998.07f
• /
• pp.1940-1943
• /
• 1998

A new PWM rectifier which offers a unity power factor is proposed. The circuit has same inductance as the conventional boosting type PWM rectifier in powering mode, but the inductance is splitted to 2 part in freewheeling mode. So the period of freewheeling mode is shorter than that of conventional boosting type PWM rectifier, and discontinuous input current is obtained in wide duty range. Therefore the proposed PWM rectifier accomplishs a unity power factor in wide range of duty ratio and boosting factor. And the conventional boosting type PWM rectifier has poor power factor near the unity boosting ratio, the proposed PWM rectifier improves this problem. The mathmatical analysis are presented and experimental results are given.