• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.38-42
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• 2006

We report 1/f noise PSD(Power Spectrum Density) of sub-100 nm MOSFETs as a function of various parameters such as HCS (Hot Carrier Stress), bias condition, temperature, device size and types of MOSFETs. The noise spectra of sub-100 nm devices showed Lorentzian-like noise spectra. We could check roughly the position of a dominant noise source by changing $V_{DS}$. With increasing measurement temperature, the 1/f noise PSD of 50 nm PMOS device decreases, but there is no decrease in the noise of NMOS device. RTN (Random Telegraph Noise) was measured from the device that shows clearly a Lorentzian-like noise spectrum in 1/f noise spectrum.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.56-62
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• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.459-462
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• 2019

This work presents methods for reducing overshoot voltages across the drain-source of silicon carbide (SiC) MOSFETs in grid-connected hybrid active neutral-point-clamped (ANPC) inverters. Compared with 3-level NPC-type inverter, the hybrid ANPC inverter can realize the high efficiency. However, SiC MOSFETs conduct its switching operation at high frequencies, which cause high overshoot voltages in such devices. These overshoot voltages should be reduced because they may damage switching devices and result in electromagnetic interference (EMI). Two major strategies are used to reduce the overshoot voltages, namely, adjusting the gate resistor and using a snubber capacitor. In this paper, advantages and disadvantages of these methods will be discussed. The effectiveness of these strategies is verified by experimental results.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.19 no.9
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• pp.47-52
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• 2020

With the 4th industrial revolution, condition monitoring using machine learning techniques has become popular among researchers. An overload due to complex operations causes several irregularities in MOSFETs. This study investigated the acquired voltage to analyze the overcurrent effects on MOSFETs using a failure mode effect analysis (FMEA). The results indicated that the voltage pattern changes greatly when the current is beyond the threshold value. Several features were extracted from the collected voltage signals that indicate the health state of a switched-mode power supply (SMPS). Then, the data were reduced to a smaller sample space by using a principal component analysis (PCA). A robust machine learning algorithm, the support vector machine (SVM), was used to classify different health states of an SMPS, and the classification results are presented for different parameters. An SVM approach assisted by a PCA algorithm provides a strong fault diagnosis framework for an SMPS.

• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.33-37
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• 2017

This paper suggests a new reliable push pull converter. The proposed push-pull converter have additional two diodes comparing with conventional push-pull converter. When one of two MOSFETs of the push-pull converter is on state, the other MOSFET is automatically off state due to adding additional diodes. Therefore, the converter is under electric noise environments, the converter avoids short circuit due to turning on of two MOSFETs. In this paper, the suggested converter has been simulated by PLECS software for 100 kHz switching frequency. In simulation, the current of the converter switches increases about 10 % for $20{\mu}sec$ electric noise environments. However, the converter operates very reliably without any short circuit conditions.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.266-269
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• 2000

This paper presents a novel single-stage unity power factor converter which features the reduced switching losses by zero-voltage switching and zero-current switching (ZVZCS). Hence the turn-on and turn-off losses of switches are sufficiently reduced. And the reduced conduction losses are achieved by the elimination of one leg of front-end rectifier. And low on-resistance MOSFETs (Synchronous Rectifier) are used in the rectifier at the secondary side of high frequency transformer instead of diodes. Theoretical analysis simulated results of a AC to DC 150W(5V, 30A) converter are presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Journal of Power Electronics
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• v.10 no.4
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• pp.335-341
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• 2010

In this paper, an interleaved soft switching boost converter for a Photovoltaic Power Conditioning System (PV-PCS) with high efficiency is proposed. In order to raise the efficiency of the proposed converter, a 2-phase interleaved boost converter integrated with soft switching cells is used. All of the switching devices in the proposed converter achieve zero current switching (ZCS) or zero voltage switching (ZVS). Thus, the proposed circuit has a high efficiency characteristic due to low switching losses. To analyze the power losses of the proposed converter, two experimental sets have been built. One consists of normal devices (MOSFETs, Fast Recovery (FR) diodes) and the other consists of advanced power devices (CoolMOSs, SiC-Schottky Barrier Diodes (SBDs)). To verify the validity of the proposed topology, theoretical analysis and experimental results are presented.

• Journal of Power Electronics
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• v.13 no.2
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• pp.177-185
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• 2013

This paper studies a soft switching DC/DC converter to achieve zero voltage switching (ZVS) for all switches under a wide range of load condition and input voltage. Two three-level PWM circuits with the same power switches are adopted to reduce the voltage stress of MOSFETs at $V_{in}/2$ and achieve load current sharing. Thus, the current stress and power rating of power semiconductors at the secondary side are reduced. The series-connected transformers are adopted in each three-level circuit. Each transformer can be operated as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer from the input side to the output side. Therefore, no output inductor is needed at the secondary side. Two center-tapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Due to the resonant behavior by the resonant inductance and resonant capacitance at the transition interval, all switches are turned on at ZVS. Experiments based on a 1kW prototype are provided to verify the performance of proposed converter.