• ETRI Journal
• /
• v.20 no.1
• /
• pp.37-45
• /
• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.13 no.2
• /
• pp.47-52
• /
• 2013

A novel architecture to reduce dramatically the coupling length of multimode interference-based couplers (MMICs) is proposed by replacing conventionally designed MMICs by cascaded two-section plasmonic stepped MMICs (PS-MMIC). For the 60% cross power splitting ratio in a stepped-width MMIC, the coupling length of device results in around 42% length reduction. Furthermore, the power splitting ratio and coupling length of plasmonic MMIC just vary around 1~2% along the variation of refractive index. On the contrast, those factors for the variation of MMIC's width strongly vary around 30~40%.

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.4
• /
• pp.1-9
• /
• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.9
• /
• pp.911-915
• /
• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.2
• /
• pp.191-197
• /
• 2017

According to the ubiquitous usage of smartphone, so many smartphone applications have been developed, and especially data communications and position measurement technologies without additional equipments have been developed using acoustic signal. But there is a limitation to select the frequency of the acoustic signal due to the smartphone hardware, and there is non-linearity in the electronic circuits in a sound generation devices, the audible sound generated from the speaker is not avoidable. And it causes critical difficulty to the commercial system deployment. In this paper, a simulation technique to calculate the power of the audible acoustic signal by human is applied to several types of acoustic signals to evaluate the loudness. These could be referred when the acoustic communications or positioning systems are designed, for the purposed of inaudible sounding to human.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.29 no.3
• /
• pp.579-588
• /
• 2019

Industrial control systems consist of various physical devices such as sensors, actuators. Security Infringement such as waterworks facilities Remote Access Infringement and power control systems Infection have been occured by vulnerability of Access Control. Access control to physical devices must be fulfilled with a reliable system. However, Having a single access control system inside company can not guarantee reliability. In addition, when single access control is struggled with error or infringement, access control system is totally unavailable. so system requires a additional access control method or system. In this paper, we proposed access control mechanism for reliable and stable operation using blockchain and smart contract. Proposed Mechanism using trust score to consider resources to be consumed depending on each industrial environment in consideration of the industrial control system where availability is more important than integrity and confidentiality. Unlike other blockchain-based access control system, proposed system is designed for the currently operating industrial control system.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.129-140
• /
• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.4
• /
• pp.292-297
• /
• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.5
• /
• pp.423-432
• /
• 2023

With the increasing demand for mobile devices featuring multi-touch operation, extensive research is being conducted on touch screen panel (TSP) Readout ICs (ROICs) that should possess low power consumption, compact chip size, and immunity to external noise. Therefore, this paper discusses capacitive touch sensors and their readout circuits, and it introduces research trends in various circuit designs that are robust against external noise sources. The recent state-of-the-art TSP ROICs have primarily focused on minimizing the impact of parasitic capacitance (Cp) caused by thin panel thickness. The large Cp can be effectively compensated using an area-efficient current compensator and Current Conveyor (CC), while a display noise reduction scheme utilizing a noise-antenna (NA) electrode significantly improves the signal-to-noise ratio (SNR). Based on these achievements, it is expected that future TSP ROICs will be capable of stable operation with thinner and flexible Touch Screen Panels (TSPs).