• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.2
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.437-444
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• 2010

The audio data have been communicated using analog methods or simple protocols. However, with the advent and improvement of various multimedia functions, many audio devices have been integrated into a mobile handset in which interconnection lines are very complicated. Conventional point-to-point connections such as $I^2S$ and PCM demand more power consumption whenever more devices are attached. In this paper, we design a common bus digital audio interface that communicates with only two wires and employs the clock gear method to reduce bus power consumption. The comparison results show that the proposed common bus connection can reduce more than 30% of power consumption as compared with point-to-point connection if more than three devices are connected.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.1-10
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• 1999

A low power concumption 2.4 GHz one-chip transceiver MMIC was designed and fabricated using $1.0\mu\textrm{m}$ ion-implantation MESFET process and packaged on a 24 lead SSOP. In the transmitter mode, it revealed conversion gain of 7.5 dB, output IP3 of -3.5 dBm, and noise figure of 3.9 dB at 2.44 GHz with 3.9 mA current consumption. In the receiver mode, it revealed voltage sensitivity of 6.5 mV/$\mu\$W with 2 .0 mA current consumption. Comparing the fabricated MMIC with the results of MMICs reported elsewhere, it was shown that the fabricated MMIC had good performance. The low power consumption 2.4 GHz transceiver MMIC is expected to be used for various applications such as wireless local area networks, wireless local loops and RFID tags in ISM-band.

• Journal of the Korea Society of Computer and Information
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• v.23 no.10
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• pp.65-72
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• 2018

In this paper, we used LSTM as a method to detect abnormal behavior of motors. We fixed the high layout size to 1 and changed the range of the input values and the neural network structure to see what change in power consumption prediction. Now, as the fourth industrial revolution era, smart factories are attracting attention. All the physical actions of smart factories are done using motors. Continuous monitoring of motor malfunctions helps to detect malfunctions and efficient operation. However, it is difficult to acquire the power consumption constantly due to the influence of the noise. We have experimented with a simple experimental environment, a method of predicting similarity to input data by adjusting the range of the input data or by changing the neural network structure.

• Environmental and Resource Economics Review
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• v.18 no.2
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• pp.191-215
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• 2009

In the real world, there exist various products in terms of price and quality, and it can be expected that a product with lower price and higher quality than others is better. Hence efficiency of consumption behaviour can be measured by the level of goodness in terms of price and quality attributes of that product. The purpose of this research is to define consumption efficiency in terms of price and quality, and to measure consumption efficiency of IT and electronic products in South Korea. From the results, many consumers have purchased inefficient products m air-conditioner, TV, digital camera, MP3 player, computer markets. On the other hand, consumers have purchase efficient products in refrigerator and washing machine markets relatively. In addition, we analyze the relationship of consumption efficiency, information channel, and electric power consumption. This research may provide meaningful information for consumer's behaviour by measuring consumption efficiency quantitatively.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2269-2270
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• 2008

Zigbee that is the wireless personal area networks communication technology for low power consumption is low-cost, low-power consumption, and small size and program code. From the present paper symbol and chip sequence of existing Zigbee module undergarment PN code generators which are a 1:1 mapping method it uses shift register and it plans the method which it proposes. The experimental result used Xilinx ISE and it measured synthesis and timing and power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4B
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• pp.412-421
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• 2011

An economic ship routing means to sail a ship with a goal of minimizing the fuel consumption by utilizing weather forecast information, and many such systems have been recently developed. Most of them assume that sailing is carried out with a constraint like a fixed output of engine-power or a fixed sailing speed. However, if the output of engine-power is controlled, it is possible to reduce the fuel consumption by sailing a ship under a relatively good weather condition. In this paper, we propose a novel economic ship routing system which can search optimal outputs of the engine-power for each part of a path by employing an evolutionary strategy. In addition, we develope an $A^*$ algorithm to find the shortest path and a method to enhance the degree of curve representation. These make the proposed system applicable to an arbitrary pair of departure and destination points. We compared our proposed system with another existing system not controlling output of the engine-power over 36 scenarios in total, and observed that the former reduced the estimated fuel consumption than the latter by 1.3% on average and the maximum 5.6% with little difference of estimated time of arrival.