• Proceedings of the KSR Conference
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• 1999.11a
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• pp.318-325
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• 1999

Modern AC electric car has PWM(Pulse Width Modulation)-controlled converters, which give rise to higher harmonics. The current harmonics injected from AC electric car is propagated through power feeding circuit, As the feeding circuit is a distributed constant circuit composed of RLC, the capacitance of the feeding circuit and the inductance on the side of power system cause a parallel resonance and a magnification of current harmonics at a specific frequency. The magnified current harmonics usually brings about various problems. That is, the current harmonics makes interference in the adjacent lines of communications and the railway signalling system. Furthermore, in case it flows on the side of power system, not only overheating and vibration at the power capacitors but also wrong operation at the protective devices can occur. Therefore, the exact assessment of the harmonic current flow must be undertaken at design and planning stage for the electric traction systems. From these point of view, this study presents an approach to model and to analyse traction power feeding system focused on the amplification of harmonic current The proposed algorithm is applied to a standard AT(Auto-transformer)-fed test system in which electric car with PWM-controlled converters is running.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.832-835
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• 2003

This paper presents a design and characteristics analysis of a SRM drive for EPS(Electrically Power Steering) application. A conventional driving room space and mechanical structure are suggested in design stage. In the restricted design conditions, motor parameters are determined for sufficient torque and speed. For the smooth torque generation and simple circuit of power system, 12/8 motor drive is considered. With FEM and magnetic circuit analysis, designed motor is simulated to meet the requirement of specifications. Effectiveness of the suggested SRM drive for EPS application is verified by the manufactured prototype motor drive tests.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.100-106
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• 2024

To generate the plasma required in dry cleaning processes, the plasma chamber must be supplied with a high-quality AC voltage with a voltage of more than 1 kV and a frequency of 400 kHz. In the existing research, many methods to supply high power have been studied, but how to improve the quality of the power for high-quality plasma has been relatively little studied. In this paper, we propose a study to improve the quality of RF power circuit for high-quality plasma generation in dry cleaning method. Existing methods in the environment of full-bridge-based RF power circuits must perform PWM duty control in the light load region. This causes distortions in the waveform, resulting in poor power quality, which directly leads to poor plasma quality. To solve these problems, a half-bridge switching method is proposed and the improvement in waveform quality is verified. To verify the feasibility of the design and control algorithm proposed in this paper, an RF power circuit prototype is fabricated and the proposed design and control method is verified through simulation and actual experiments under dummy load.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1081-1090
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• 2013

In this paper, a C-band 10 W power amplifier with internally matched input and output matching circuit is designed and fabricated. The used power transistor for the power amplifier is GaAs pHEMT bare-chip. The wire bonding analysis considering the size of the capacitor and the position of transistor pad improves the accurate design. The matching circuit design with the package effect using EM simulation is performed. To reduce the unsymmetry of IMD3 in 2-tone measurement due to the memory effect, the bias circuit minimizing the memory effect is proposed and employed. The measured $P_{1dB}$, power gain, and power added efficiency are 39.8~40.4 dBm, 9.7~10.4 dB, and 33.4~38.0 %, respectively. Adopting the proposed bias circuit, the difference between the upper and lower IMD3 is less than 0.76 dB.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.101-106
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• 2022

In this paper, WBG semiconductor such as SiC and GaN were applied as power switches for LCL circuit that can be applied to satellite power systems and the test results of the LCL circuit are reported. P-channel MOSFET and N-channel MOSFET, which were generally used in the conventional LCL circuit, were applied together to expand the utility of the test results. The design and stability evaluation were performed using a Micro Cap circuit simulation program. For the test circuit, a module using each switch was manufactured, and a total of 5 modules were manufactured and the steady state and transient state characteristics were compared. From the experimental results, the LCL circuit for power supply of the satellite power system constructed in this paper satisfied the constant current and constant voltage conditions under various operating conditions. The P-channel MOSFET showed the lowest efficiency characteristics, and the three N-channel switches of Si, SiC and GaN showed relatively high efficiency characteristics of up to 99.05% or more. In conclusion, it was verified that the on-resistor of the switch had a direct effect on the efficiency and loss characteristics.

• Proceedings of the KIEE Conference
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• 2002.11b
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• pp.80-82
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• 2002

To solve the difficulty in obtaining transmission routes and substation sites. increase the transmission capacity between generation sites and load centers. and enhance the stability of the power system. we have constructed and operated the 765kV double circuit transmission line(hereunder T/L) from the Dangjin thermal power plant and the Uljin nuclear power plant to the metropolitan. It makes it possible for us to accumulate know-how of the 765kV system that is the highest operating system level in Asia. As the second 765kV project, we are going to construct the 765kV single circuit T/L between Ansung and Gap yung. Because of the different electrical and mechanical characteristics. we are in need of different design technology. This paper presents the optimal design of 765kV single circuit transmission line after due consideration about the arrangement of conductors. the shape of a tower, insulation, etc.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.143-149
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• 2018

It has become ever harder to design reliable circuits with each nanometer technology node; under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Therefore, circuit designers need to consider these reliability effects in the early stages of design to make sure there are enough margins for circuits to function correctly over their entire lifetime. However, such an approach excessively increases the size and power dissipation of a system. As the impact of reliability, new techniques in designing aging-resilient circuits are necessary to reduce the impact of the aging stresses on performance, power, and yield or to predict the failure of a system. Therefore, in this paper, a novel low power on-chip self-tuning circuit considering the aging effects has been proposed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.1
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• pp.102-106
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• 2009

This paper presents the design and optimization of output matching network according to envelope for class F power amplifier(PA) which is to apply to envelope elimination and restoration(EER) transmitter. In this paper, to increase the PAE of class F power amplifier which applies to EER transmitter, the varactor diode has been used on output matching network. As envelope changes, it optimizes constitution of harmonic trap that is short circuit in 2nd-harmonic and is open circuit in 3rd-harmonic. When drain voltage changes from 25 V to 30 V, some percentage is improved in the PAE.put the abstract of paper here.

• Journal of IKEEE
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• v.11 no.2
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• pp.83-88
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• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.