• Journal of the Korean Chemical Society
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• v.47 no.6
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• pp.608-613
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• 2003

In order to remove particles on surface of post-oxide CMP wafer, new cleaning solution was prepared by mixing with DHF (Diluted HF), nonionic surfactant PAAE (Polyoxyethylene Alkyl Aryl Ether), DMSO (Dimethylsulfoxide) and D.I.W.. Silicone wafers were intentionally contaminated by silica, alumina and PSL (polystylene latex) which had different zeta potentials in cleaning solution. This cleaning solution under megasonic irradiation could remove particles and metals simultaneously at room temperature in contrast to traditional AMP (mixture of $NH_4OH,\;H_2O_2$ and D.I.W) without any side effects such as increasing of microroughness, metal line corrosion and deposition of organic contaminants. This suggests that this cleaning solution would be useful future application with copper CMP in brush cleaning process as well as traditional post CMP cleaning process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.223-227
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• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.501-504
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• 1999

In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.17-23
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• 2002

The more productive and stable fabrication can be obtained by applying chemical mechanical polishing (CMP) process to shallow trench isolation (STI) structure in 0.18 $\mu\textrm{m}$ semiconductor device. However, STI-CMP process became more complex, and some kinds of defect such as nitride residue, tern oxide defect were seriously increased. Defects like nitride residue and silicon damage after STI-CMP process were discussed to accomplish its optimum process condition. In this paper, we studied how to reduce torn oxide defects and nitride residue after STI-CMP process. To understand its optimum process condition, We studied overall STI-related processes including trench depth, STI-fill thickness and post-CMP thickness. As an experimental result showed that as the STI-fill thickness becomes thinner, and trench depth gets deeper, more tern oxide were found in the CMP process. Also, we could conclude that low trench depth whereas high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.171-174
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• 2000

We have investigated the CMP slurry properties of silicate oxide thin films surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-ortho-silicate glass(PE-TEOS), $O_3$ boro-phospho silicate giass( $O_3$-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray Fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing, which is due to a CMP slurry. The polished $O_3$-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.59-59
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• 2009

현재 CMP분야는 광역 평탄화 반도체 소자의 집적화 및 소형화가 진행됨에 따라서 CMP 공정의 중요성은 날로 성장하고 있다. 하지만 이러한 CMP공정은 불가피하게도 scratch, pit, CMP residue와 같은 defect들을 발생시키고 있으며, 점점 선폭이 작아짐에 따라, 이러한 defect들이 반도체 수율에 미치는 영향은 심각해지고 있다. Defect들 중에 특히 scratch는 반도체에 치명적인 circuit failure를 일으키게 된다. 또한 반도체 내구성과 신뢰성을 감소시키게 되고, 누전전류를 증가시키는 등 바람직하지 못한 현상들이 생기게 된다. 본 연구에서는 scratch 와 같은 deflect들을 효율적으로 검출, 분석하고, scratch를 감소시키는데 그 목적이 있다. 본 실험을 위해 8" TEOS wafer와 commercial oxide slurry 및 friction polisher (Poli-500, G&P tech., Korea)를 사용하여 CMP 공정을 진행하였으며, CMP 공정조건은 각각 80rpm/80rpm/1psi(Platen speed/Head speed/Pressure)에서 1분 동안 연마를 한 후 scratch 발생 경향을 살펴보았다. CMP 후 wafer위에 오염되어 있는 slurry residue들을 제거하기 위해 SC-1, HF 세정을 이용하여 최적화된 post-CMP 공정기술을 제안하였다. Scratch 검출 및 분석을 위해 wafer surface analyzer (Surfscan 6200, Tencor, USA)와 optical microscope (LV100D, Nicon, Japan)를 사용하였다. CMP 공정 변수들에 따른 scratch 발생정도를 비교하였으며, scratch 발생 요인들에 따른 scratch 형태 및 발생정도를 살펴보았다. 최적화된 post-CMP 세정 조건은 메가소닉과 함께 SC-1 세정을 실시하여 slurry residue들을 제거한 후, HF 세정을 실시하여 잔여 오염물들을 제거하고 검출이 용이하도록 scratch를 확장시킬 수 있도록 제안하였으며, 100%의 particle removal efficiency (PRE)를 얻을 수 있었다. 실제 CMP 공정후 post-CMP 세정 단계별 scratch 개수를 측정한 결과, SC-1 세정 후 약 220개의 scratch가 검출되었으며, 검출되지 않았던 scratch가 HF 세정 후 확장되어 드러남에 따라 약 500개의 scratch 가 검출되었다.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.45-49
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• 2004

We examined large particles and filter size effects of Central Chemical Supplying (CCS) system for STI-CMP on Light Point Defects (LPDs) after polishing. As manufacturing process recently gets thinner below 0.1 um line width, it is very important to keep down post-CMP micro-scratch and LPDs in case of STI-CMP. Therefore, we must control the size distribution of large particles in a slurry. With optimization of final filter size, CCS system is one of the solutions for this issue. The oxide and nitride CMP tests were accomplished using nano-ceria slurries made by ourselves. The number of large particles in a slurry and the number of LPDs on the wafer surface after CMP were reduced with decrease of the final filter size. Oxide removal rates slightly changed according to the final filter size, showing the good performance of self-made nano ceria slurries.