• Journal of Sensor Science and Technology
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• v.7 no.1
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• pp.73-82
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• 1998

In silicon surface micro-machining, the newly developed GPE(gas-phase etching) process was verified as a very effective method for the release of highly compliant micro-structures. The developed GPE system with anhydrous HF gas and $CH_{3}OH$ vapor was characterized and the selective etching properties of sacrificial layers to release silicon micro-structures were discussed. P-doped polysilicon and SOI(silicon on insulator) substrate were used as a structural layer and TEOS(tetraethyorthdsilicate) oxide, thermal oxide and LTO(low temperature oxide) as a sacrificial layer. Compared with conventional wet-release, we successfully fabricated micro-structures with virtually no process-induced striction and residual product.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.402-406
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• 2004

$WSi_2$, $TiSi_2$, $CoSi_2$, and $TaSi_2$ are general silicides used today in semiconductor devices. $WSi_2$ thin films have been proposed, studied and used recently in CMOS technology extensively to reduce sheet resistance of polysilicon and $n^{+}$ region. However, there are several serious problems encountered because $WSi_2$ is oxidized and forms a native oxide layer at the interface between $WSi_2$ and $Si_3$$N_4$. In this study, we have introduced 20 $slm-N_2$ gas from top to bottom of the furnace in order to control native oxide films between $WSi_2$ and $Si_3$$N_4$ film. In resulting SEM photographs, we have observed that the native oxide films at the surface of $WSi_2$ film are removed using the long injector system.

• Journal of Sensor Science and Technology
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• v.12 no.4
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• pp.149-155
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• 2003

A PMOSFET photodetector for highly-sensitive active pixel sensor(APS) is presented. This sensor uses 5V power supply and has been designed and fabricated using I-poly and 2-metal $1.5{\mu}m$ CMOS technology. The feature of a PMOSFET photodetector is that the polysilicon gate of the PMOSFET was connected to n-well, in order to increase the photo sensitivity. The designed MOS photodetector has similar $I_{DS}-V_{DS}$ characteristics with a standard MOSFET. One dimensional image sensor with 16 pixels based on the PMOSFET photodetector has also been designed and fabricated. Unit pixel of the designed sensor consists of a PMOSFET photodetector and 4 NMOSFETs. Unit pixel area is $86{\mu}m{\times}90.5{\mu}m$ and its fill factor is about 12%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.808-812
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• 2006

In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• Journal of Sensor Science and Technology
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• v.12 no.5
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• pp.218-224
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• 2003

The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, $H_2$ and $H_2$/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage($V_{th}$), subthreshold slope(S) and maximum transconductance($G_m$) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.

• Journal of Sensor Science and Technology
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• v.5 no.5
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• pp.31-37
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• 1996

This paper presents characteristics of pressure sensor using shear-type piezoresistor of LPCVD(low pressure chemical vapour deposition) grown polycrystalline silicon films. The sensor has 3.1mV/V of pressure sensitivity in the pressure range of $1kgf/cm^{2}$, ${\pm}0.012%FS/^{\circ}C$ of TCO, and ${\pm}0.08%FS/^{\circ}C$ of TCS in the temperature range of $-20{\sim}+125^{\circ}C$. It showed ${\pm}0.2%FS$ of hysteresis and ${\pm}1.5%FS$ of non-linearity. Shear-type polycrystalline silicon pressure sensor can eliminate temperature dependence of offset caused by resistors mismatch and be used in relatively wide temperature range, compared to the conventional full-bridge silicon pressure sensors.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.615-620
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• 2008

We fabriacted thermal evaporated $10nm-Ni_{1-x}Co_x$(x=0.2, 0.6, and 0.7) films on 70 nm-thick polysilicon substrate with $0.5{\mu}m$ line width. NiCo composite silicide layers were formed by rapid thermal annealing (RTA) at the temperatures of $700^{\circ}C$ and $1000^{\circ}C$. Then, we checked the microstructure evaluation of silicide patterns. A FIB (focused ion beam) was used to micro-mill the interconnect patterns with low energy condition (30kV-10pA-2 sec). We investigated the possibility of selective removal of silicide layers. It was possible to remove low resistance silicide layer selectively with the given FIB condition for our proposed NiCo composite silicides. However, the silicides formed from $Ni_{40}Co_{60}$ and $Ni_{30}Co_{70}$ composition showed void defects in interconnect patterns. Those void defects hinder the selective milling for the NiCo composite silicides.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1615-1622
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• 2008

We have fabricated the poly-silicon thin film transistor(TFT) which has the LDD-region with graded spacer. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $H_2$/plasma processes were fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring/analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplicities of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2001.11a
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• pp.68-68
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• 2001

Thin films of polycrystalline silicon (poly-Si) is a promising material for use in large-area electronic devices. Especially, the poly-Si can be used in high resolution and integrated active-matrix liquid-crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs) because of its high mobility compared to hydrogenated _amorphous silicon (a-Si:H). A number of techniques have been proposed during the past several years to achieve poly-Si on large-area glass substrate. However, the conventional method for fabrication of poly-Si could not apply for glass instead of wafer or quartz substrate. Because the conventional method, low pressure chemical vapor deposition (LPCVD) has a high deposition temperature ($600^{\circ}C-1000^{\circ}C$) and solid phase crystallization (SPC) has a high annealing temperature ($600^{\circ}C-700^{\circ}C$). And also these are required time-consuming processes, which are too long to prevent the thermal damage of corning glass such as bending and fracture. The deposition of silicon thin films on low-cost foreign substrates has recently become a major objective in the search for processes having energy consumption and reaching a better cost evaluation. Hence, combining inexpensive deposition techniques with the growth of crystalline silicon seems to be a straightforward way of ensuring reduced production costs of large-area electronic devices. We have deposited crystalline poly-Si thin films on soda -lime glass and SiOz glass substrate as deposited by PVD at low substrate temperature using high power, magnetron sputtering method. The epitaxial orientation, microstructual characteristics and surface properties of the films were analyzed by TEM, XRD, and AFM. For the electrical characterization of these films, its properties were obtained from the Hall effect measurement by the Van der Pauw measurement.