• Title/Summary/Keyword: Polysilicon

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Characteristics and Microstructure of Co/Ni Composite Silicides on Polysilicon Substrates with Annealing Temperature (폴리실리콘 기판 위에 형성된 코발트 니켈 복합실리사이드 박막의 열처리 온도에 따른 물성과 미세구조변화)

  • Kim, Sang-Yeob;Song, Oh-Sung
    • Korean Journal of Materials Research
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    • v.16 no.9
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    • pp.564-570
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    • 2006
  • Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

An Analysis on the Leakage Current of Drain-offset Poly-Si TFT′s (드레인오프셋트 다결정실리콘 박막트랜지스터의 누설전력 해석)

  • 이인찬;김정규;마대영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.2
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    • pp.111-116
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    • 2001
  • Poly-Si TFT's(Polysilicon thin filmtransistors) have been actively studied due to their applications in active matrix liquid crystal displays and active pull-up devices of CMOS SRAM's. For such applications, the leakage current has to be in the range of sub-picoampere. However, poly-Si TFT's suffer from anomalous high leakage currents, which is attributed to the emission of the traps present at gain boundaries in the drain junction. The leakage current has been analyzed by the field emission via grain-boundary traps and thermionic field emission over potential barrier located at the grain boundary. We found that the models proposed before are not consistent with the experimental results at far as drain-offset poly-Si TFT's we fabricated concern. In this paper, leakage current of drain-offset poly-Si TFT's with different offset lengths was studied. A conduction model based on the thermionic emission of the tunneling electrons is developed to identify the leakage mechanism. It was found that the effective grain size of the drain-offset region is important factor in the leakage current. A good agreement between experimental and simulated results of the leakage current is obtained.

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Analysis of PMOS Capacitor with Thermally Robust Molybdenium Gate (열적으로 강인한 Molybdenium 게이트-PMOS Capacitor의 분석)

  • Lee, Jeong-Min;Seo, Hyun-Sang;Hong, Shin-Nam
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.7
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    • pp.594-599
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    • 2005
  • In this paper, we report the properties of Mo metal employed as PMOS gate electrode. Mo on $SiO_2$ was observed to be stable up to $900^{\circ}C$ by analyzing the Interface with XRD. C-V measurement was performed on the fabricated MOS capacitor with Mo Bate on $SiO_2$. The stability of EOT and work-function was verified by comparing the C-V curves measured before and after annealing at 600, 700, 800, and $900^{\circ}C$. C-V hysteresis curve was performed to identify the effect of fired charge. Gate-injection and substrate-injection of carrier were performed to study the characteristics of $Mo-SiO_2$ and $SiO_2-Si$ interface. Sheet resistance of Mo metal gate obtained from 4-point probe was less than $10\;\Omega\Box$ that was much lower than that of polysilicon.

Field Emission properties of Porous Polycrystalline silicon Nano-Structure (다결정 다공질 실리콘 나노구조의 전계 방출 특성)

  • Lee, Joo-Won;Kim, Hoon;Park, Jong-Won;Lee, Yun-Hi;Jang, Jin;Ju, Byeong-Kwon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.04b
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    • pp.69-72
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    • 2002
  • We establish a visible light emission from porous polycrystalline silicon nano structure(PPNS). The PPNS layer are formed on heavily doped n-type Si substrate. 2um thickness of undoped polycrystalline silicon deposited using LPCVD (Low Pressure Chemical Vapor Deposition) anodized in a HF: ethanol(=1:1) as functions of anodizing conditions. And then a PPNS layer thermally oxidized for 1 hr at $900^{\circ}C$. Subsequently, thin metal Au as a top electrode deposited onto the PPNS surface by E-beam evaporator and, in order to establish ohmic contact, an thermally evaporated Al was deposited on the back side of a Si-substrate. When the top electrode biased at +6V, the electron emission observed in a PPNS which caused by field-induces electron emission through the top metal. Among the PPNSs as functions of anodization conditions, the PPNS anodized at a current density of $10mA/cm^{2}$ for 20 sec has a lower turn-on voltage and a higher emission current. Furthermore, the behavior of electron emission is uniformly maintained.

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Design and Fabrication of Silicon Flow Sensor For Detecting Air Flow (유속 감지를 위한 실리콘 유량센서의 설계 및 제작)

  • 이영주;전국진;부종욱;김성태
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.5
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    • pp.113-120
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    • 1994
  • Silicon flow sensor that can detect the velocity and direction of air flow was designed and fabricated by integrated circuit process and bulk micromachining technique. The flow sensor consists of three-layered dielectric diaphragm, a heater at the center of the diaphragm, and four thermopiles surrounding the heater at each side of diaphragm as sensing elements. This diaphragm structure contributes to improve the sensitivity of the sensor due to excellent thermal isolation property of dielectric materials and their tiny thickness. The flow sensor has good axial symmetry to sense 2-D air flow with the optimized sensing position in the proposed structure. The sensor is fabricated using CMOS compatible process followed by the anisotropic etching of silicon in KOH and EDP solutions to form I$\mu$ m thick dielectric diaphragm as the last step. TCR(Temperature Coefficient of Resistance) of the heater of the fabricated sensors was measured to calculate the operating temperature of the heater and the output voltage of the sensor with respect to flow velocity was also measured. The TCR of the polysilicon heater resistor is 697ppm/K, and the operating temperature of the heater is 331$^{\circ}C$ when the applied voltage is 5V. Measured sensitivity of the sensor is 18.7mV/(m/s)$^{1/2}$ for the flow velocity of smaller than 10m/s.

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Consideration of CCD Gate Structure in the Determination of the Point Spread Function of Yohkoh Soft X-Ray Telescope (SXT)

  • Shin, Jun-Ho;Sakurai, Takashi
    • The Bulletin of The Korean Astronomical Society
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    • v.37 no.1
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    • pp.93.2-93.2
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    • 2012
  • Point Spread Function (PSF) is one of the most important optical characteristics for describing the performance of a telescope. And a concept of subpixelization is inevitable in evaluating the undersampled PSF (Shin and Sakurai 2009). Then, the internal structure of Yohkoh SXT CCD pixel is not uniform: For the top half of pixel area, the X-ray should pass a so-called gate structure where the charges are transferred to an output amplifier. This gate structure shows energy-dependent sensitivity (Tsuneta et al. 1991). For example, for Al-K (8.34 A) X-ray emission, the transmission of the polysilicon gate is about 0.9. Also, for the peak coronal response of the SXT thin filters, around 17 angstrom (0.729 keV), the transmission of the gate is about 0.6, falling off sharply towards longer wavelengths. It should be noted that this spectrally dependent non-uniform response of each CCD pixel will certainly have a noticeable effect on the properties of the PSF at longer wavelengths. Therefore, especially for analyzing the undersampled PSF of low energy source, a careful consideration of non-uniform internal pixel structure is required in determining the shape of the PSF core. The details on the effect of gate structure will be introduced in our presentation.

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Design, Fabrication and Micromachining Error Evaluation for a Surface-Micromachined Polysilicon Capacitice Accelerometer (표면미세가공기술을 이용한 수평감지방식의 정전용량형 다결정 실리콘 가속도계의 설계, 제작 및 가공 오차 영향 분석)

  • Kim, Jong-Pal;Han, Gi-Ho;Jo, Yeong-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.25 no.3
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    • pp.529-536
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    • 2001
  • We investigate a surface-micromachined capacitive accelerometer with the grid-type electrodes surrounded by a perforated proof-mass frame. An electromechanical analysis of the microaccelerometer has been performed to obtain analytical formulae for natural frequency and output sensitivity response estimation. A set of prototype devices has been designed and fabricated based on a 4-mask surface-micromachining process. The resonant frequency of 5.8$\pm$0.17kHz and the detection sensitivity of 0.28$\pm$0.03mV/g have been measured from the fabricated devices. The parasitic capacitance of the detection circuit with a charge amplifier has been measured as 3.34$\pm$1.16pF. From the uncertainty analysis, we find that the major uncertainty in the natural frequency of the accelerometer comes from the micromachining error in the beam width patterning process. The major source of the sensitivity uncertainty includes uncertainty of the parasitic capacitance, the inter-electrode gap and the resonant frequency, contributing to the overall sensitivity uncertainty in the portions of 75%, 14% and 11%, respectively.

Laterally-Driven Electrostatic Repulsive-Force Microactuator (수평구동형 정전반발력 마이크로액추에이터)

  • Lee, Gi-Bang;Jo, Yeong-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.25 no.3
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    • pp.424-433
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    • 2001
  • We present a new electrostatic repulsive-force microactuator using a lateral repulsive force induced by an asymmetric distribution of electrostatic field. The lateral repulsive force has been characterized by a simple analytical equation, derived from a finite element simulation. A set of repulsive force polysilicon microactuators has been designed and fabricated by a 4-mask surface-micromachining process. Static and dynamic micromechanical behavior of the fabricated microactuators has been measured at the atmospheric pressure for a varying bias voltage. The static displacement of the fabricated microactuator, proportional to the square of the DC bias voltage, is obtained as 1.27 $\mu\textrm{m}$ for the DC bias voltage of 140V. The resonant frequency of the repulsive-force microactuator increases from 11.7 kHz to 12.7 kHz when the DC bias voltage increases from 60V to 140V. The measured quality-factor varies from 12 to 13 for the bias volatge range of 60V∼140V. The characteristics of the electrostatic repulsive-force have been discussed and compared and compared with those of the conventional electrostatic attractive-force.

Electrical and Chemical Stability of Mo Gate Electrode for PMOS (PMOS에 적합한 Mo 전극의 전기적 화학적 안정성)

  • 노영진;이충근;홍신남
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.4
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    • pp.23-28
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    • 2004
  • In this paper, the properties of Mo as PMOS gate electrodes were studied. The work-function of Mo extracted from C-V characteristic curves was appropriate for PMOS. To identify the electrical and chemical stability of Mo metal gate, the changes of work-function and EOT(Effective Oxide Thickness) values were investigated after 600, 700, 800 and 90$0^{\circ}C$ RTA(Rapid Thermal Annealing). Also it was found that Mo metal gate was stable up to 90$0^{\circ}C$ with underlying SiO$_2$through X-ray diffraction measurement. Sheet resistances of Mo metal gate obtained from 4-point probe were less than 10$\Omega$/$\square$ that was much lower than those of polysilicon.

Accurate RF Extraction Method for Gate Voltage-Dependent Carrier Velocity of Sub-0.1㎛ MOSFETs in the Saturation Region (Sub-0.1㎛ MOSFET의 게이트전압 종속 캐리어 속도를 위한 정확한 RF 추출 방법)

  • Lee, Seonghearn
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.9
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    • pp.55-59
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    • 2013
  • A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.