• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.1033-1036
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• 2002

Wafer bonding methods such as fusion and anodic bonding suffer from high temperature treatment, long processing time, and possible damage to the micro-scale sensor or actuators. In the localized bonding process, beating was conducted locally while the whole wafer is maintained at a relatively low temperature. But previous research of localized heating has some problems, such as non-uniform soldering due to non-uniform heating and micro crack formation on the glass capsule by thermal stress effect. To address this non-uniformity problem, a new heater configuration is being proposed. By keeping several points on the heater strip at calculated and constant potential, more uniform heating, hence more reliable wafer bonding could be achieved. The proposed scheme has been successfully demonstrated, and the result shows that it will be very useful in hermetic packaging. Less than 0.2 ㎫ contact Pressure were used for bonding with 150 ㎃ current input for 50${\mu}{\textrm}{m}$ width, 2${\mu}{\textrm}{m}$ height and 8mm $\times$ 8mm, 5mm$\times$5mm, 3mm $\times$ 3mm sized phosphorus-doped poly-silicon micro heater. The temperature can be raised at the bonding region to 80$0^{\circ}C$, and it was enough to achieve a strong and reliable bonding in 3minutes. The IR camera test results show improved uniformity in heat distribution compared with conventional micro heaters. For gross leak check, IPA (Isopropanol Alcohol) was used. Since IPA has better wetability than water, it can easily penetrate small openings, and is more suitable for gross leak check. The pass ratio of bonded dies was 70%, for conventional localized heating, and 85% for newly developed FP scheme. The bonding strength was more than 30㎫ for FP scheme packaging, which shows that FP scheme can be a good candidate for micro scale hermetic packaging.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.153-153
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• 2011

신 재생에너지 정책이 발전차액지원제도(Feed In Tariff; FIT)에서 신 재생에너지 의무할당제(Renewable Portfolio Standard; RPS)로 변화하면서 원별 경쟁이 가속화되고 있다. 태양광 산업 역시 이러한 환경 변화에 대처해야 하며, 그를 위한 정책 구성이 필요하다. 이에 태양광 산업 정책은 크게 두 부분으로 구분하여 진행해야 한다. 첫째, 폴리실리콘(Poly silicon)을 활용하는 다결정실리콘 태양광에너지에 초점을 맞춘 정책이며, 둘째, 미래에 상용화될 차세대 태양광 에너지에 대한 대비를 위한 연구 개발(R&D) 정책이다. 먼저 다결정실리콘 태양광에너지에 초점에서의 산업 정책은 산업육성정책과 수출정책, 인프라 구성 등으로 나눌 수 있다. 현재 과도한 국가부채로 인한 세계경제 악화로 태양광에너지 업체들의 경제성이 악화하고 있다. 더욱 빨리 그리드 패리티(Grid Parity)를 달성하기 위해 수직통합 등의 필요성이 대두하고 있다. 이에 본 연구는 그리드 패리티 달성시기를 위해 태양광 산업 내 세대 변화를 하는 경우와 하지 않는 경우를 비교하기 위해 고려할 요소를 분석하였다. 현재 신 재생에너지 가운데 태양광에너지는 타에너지원 대비 가격경쟁력을 갖추지 못한 상황이다. 그러나 수출을 고려했을 때의 향후 한국의 차세대 성장동력으로의 발전가능성이 존재한다. 따라서 가격경쟁력이 가장 중요한 영향을 미칠 신 재생에너지 의무할당제 정책 하에서 태양광에너지가 전혀 채택되지 않는 상황을 막기 위한 정책이 필요하다. 그를 위해 필요한 정책적 요소들을 알아보았다. 마지막으로 인프라 구성을 위해 태양광 산업의 가치사슬(Value Chain) 상에서의 기업 분포와 경쟁력에 대한 조사를 시행하였다. 이는 태양광 산업 내의 경쟁력을 갖춘 부문과 그렇지 못한 부문을 구별하기 위함이다. 미래에 상용화될 차세대 태양광 에너지를 준비하는 과정에서는 연구개발 관련 정책이 가장 중요하게 다뤄야 할 부분이며, 그를 위해 정부 차원에서 지원하고자 하는 기술로드맵 등에 대해서 정리하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.335-335
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• 2011

Instability of a thin film attached to a compliant substrate often leads to emergence of exquisite wrinkle patterns with length scales that depend on the system geometry and applied stresses. However, the patterns that are created using the current techniques in polymer surface engineering, generally have low aspect ratio of undulation amplitude to wavelength, thus, limiting their application. Here, we present a novel and effective method that enables us to create wrinkles with a desired wavelength and high aspect ratio of amplitude over wavelength as large as to 2.5:1. First, we create buckle patterns with high aspect ratio of amplitude to wavelength by deposition of an amorphous carbon film on a surface of a soft polymer poly(dimethylsiloxane) (PDMS). Amorphous carbon films are used as a protective layer in structural systems and biomedical components, due to their low friction coefficient, strong wear resistance against, and high elastic modulus and hardness. The deposited carbon layer is generally under high residual compressive stresses (~1 GPa), making it susceptible to buckle delamination on a hard substrate (e.g. silicon or glass) and to wrinkle on a flexible or soft substrate. Then, we employ glancing angle deposition (GLAD) for deposition of a high aspect ratio patterns with amorphous carbon coating on a PDMS surface. Using this method, pattern amplitudes of several nm to submicron size can be achieved by varying the carbon deposition time, allowing us to harness patterned polymers substrates for variety of application. Specifically, we demonstrate a potential application of the high aspect wrinkles for changing the surface structures with low surface energy materials of amorphous carbon coatings, increasing the water wettability.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.158-158
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• 2011

$Cu(In_xGa_{1-x})Se_2$ (CIGS) thin film solar cell is one of the most promising solar cells in photovoltaic devices. CIGS has a direct band gap which varied from 1.0 to 1.26 eV, depending on the Ga to In ratio. Also, CIGS has been studying for an absorber in thin film solar cells due to their highest absorption coefficient which is $1{\times}10^5cm^{-1}$ and good stability for deposition process at high temperature of $450{\sim}590^{\circ}C$. Currently, the highest efficiency of CIGS thin film solar cell is approximately 20.3%, which is closely approaching to the efficiency of poly-silicon solar cell. The deposition technique is one of the most important points in preparing CIGS thin film solar cells. Among the various deposition techniques, the sputtering is known to be very effective and feasible process for mass production. In this study, CIGS thin films have been prepared by rf magnetron sputtering method using a single target. The optical and structural properties of CIGS films are generally dependent on deposition parameters. Therefore, we will explore the influence of deposition power on the properties of CIGS films and the films will be deposited by rf magnetron sputtering using CIGS single target on Mo coated soda lime glass at $500^{\circ}C$. The thickness of CIGS films will be measured by Tencor-P1 profiler. The optical properties will be measured by UV-visible spectroscopy. The crystal structure will be analyzed using X-ray diffraction (XRD). Finally the optimal deposition conditions for CIGS thin films will be developed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Journal of Environmental Health Sciences
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• v.10 no.2
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• pp.41-51
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• 1984

This study was performed using samples collected at Myungryundong and at Reservoirs. The purpose of this study was to investigate the differences of water quality between tap and raw water, and to analyse drinking water quality by Fe, Zn from corroded galvanized steel pipe. Results were as follows 1. The older the pipe was, the higher the concentration of Ferrum and Zinc was (t-test : p<0.05). Ferrum and Zinc also exceeded the limits in the older galvanized steel pipe. I think that this comes from the corrosion of pipe. 2. Mercury, Arsenic, Cadmium, Lead, Chomium, Argentum and Aurum not detected in raw water were not detected in tap water. Cobalt, Bismuth and Molybudenum detected in raw water were not detected in tap water. I think that this comes from the quality of raw water, the result of water treatment and the improbability of detection of above metals in water delivery system. 3. Silicon measured 2.4698ppm in raw water, but it ranged from 0.4769ppm to 1.982 ppm in tap water. Manganese measured 0.0638ppm in raw water, but it ranged from 0.0026ppm to 0.0198ppm in 17cases(31%) out of 55samples in tap water. I think that this comes from the water treatment. 4. Aluminium not detected in raw water was found in 17 cases (31%) out of the samples (55cases). It may be considered as the use of coagulants $Al_2(SO_4)_3$. $18H_2O$ and PAC (Poly Aluminium Chloride). The concentration of copper in tap water was much higher in 2 cases(3.6%) out of the samples(55) than that of copper in raw water. I think that this may come from the use of ${CuSO}_4$, the preventive of algae growth, and the result of chlorination, but further study must be necoessary to support the proof.

• Advances in Energy Research
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• v.1 no.2
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• pp.97-106
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• 2013

This study designs and tests a photovoltaic system with distributed maximum power point tracking (DMPPT) methodology using a field programmable gate array (FPGA) controller. Each solar panel in the distributed PV system is equipped with a newly designed DC/DC converter and the panel's voltage output is regulated by a FPGA controller using PI control. Power from each solar panel on the system is optimized by another controller where the quadratic maximization MPPT algorithm is used to ensure the panel's output power is always maximized. Experiments are carried out at atmospheric insolation with partial shading conditions using 4 amorphous silicon thin film solar panels of 2 different grades fabricated by Chi-Mei Energy. It is found that distributed MPPT requires only 100ms to find the maximum power point of the system. Compared with the traditional centralized PV (CPV) system, the distributed PV (DPV) system harvests more than 4% of solar energy in atmospheric weather condition, and 22% in average under 19% partial shading of one solar panel in the system. Test results for a 1.84 kW rated system composed by 8 poly-Si PV panels using another DC/DC converter design also confirm that the proposed system can be easily implemented into a larger PV power system. Additionally, the use of NI sbRIO-9642 FPGA-based controller is capable of controlling over 16 sets of PV modules, and a number of controllers can cooperate via the network if needed.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1938-1940
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• 2003

본 연구는 요소 센서 제작을 위한 과정으로서, 전기화학적 방법을 이용한 다공질 실리콘 구조 형성과, PDV(Physical Vapor Deposition) 법에 의한 백금 박막 코팅 및 전기화학적 전도성 고분자 코팅과 urease 고정화 단계를 고찰하고 감도 특성을 제시 하였다. 전극 기질로서 B을 도우핑한 p-type 실리콘웨이퍼를 사용하였고, HF:$C_2H_5OH:H_2O$=1:2:1의 부피비를 갖는 에칭 용액에서 5분간 -7 $mA/cm^2$의 일정 전류를 가하여 폭 2 ${\mu}m$, 깊이 10 ${\mu}m$의 다공질 실리콘(PS) 충을 형성하였다. 그 위에 200 ${\AA}$의 Ti 층을 underlayer로서 증착하고, 2000 ${\AA}$의 Pt를 중착하여 PS/Pt 박막 전극을 제작하고, 전도성 고분자로서 polypyrrole (PPy), 또는 poly(3-mehylthiophene) (P3MT)을 전기화학적으로 코팅한 후, urease(EC 3.5.1.5, type III, Jack Bean, Sigma)를 고정화 하였다. 고정화 시 전해질 수용액의 pH는 7.4로 하여 urease표면이 음전하를 갖도록 하고, 전극에 0.6 V (vs. SCE(Saturated Calomel Electrode))의 일정 전압을 가함으로써 urease가 전도성 고분자 표면에 전기적으로 흡착되도록 하였다. 이상의 방법으로 제작한 요소 센서의 감도는 PPy와 P3MT를 전자 전달 매질로 사용한 경우, 각각 8.44 ${\mu}A/mM{\cdot}cm^2$와 1.55 ${\mu}A/mM{\cdot}cm^2$의 감도를 보였다.