• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 추계학술대회 논문집
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• pp.383-384
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• 2006

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2008년도 춘계학술대회 논문집
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• pp.7-9
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• 2008

ITO thin film is generally fabricated by various. methods such as spray, CVD, evaporation, electron gun deposition, direct current electroplating, high frequency sputtering, and reactive DC sputtering. However, some problems such as peaks, bumps, large particles, and pin-holes on the surface of ITO thin film were reported, which caused the destruction of color quality, the reduction of device life time, and short-circuit. Chemical mechanical polishing (CMP) process is one of the suitable solutions which could solve the problems

• 열처리공학회지
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• 제34권2호
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• pp.75-80
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• 2021

The crystal grains of polycrystalline diamond vary depending on deposition conditions and growth thickness. The diamond thin film deposited by the CVD method has a very rough growth surface. On average, the surface roughness of a diamond thin film deposited by CVD is in the range of 1-100 um. However, the high surface roughness of diamond is unsuitable for application in industrial applications, so the surface roughness must be lowered. As the surface roughness decreases, the scattering of incident light is reduced, the heat conduction is improved, the mechanical surface friction coefficient can be lowered, and the transmittance can also be improved. In addition, diamond-coated cutting tools have the advantage of enabling ultra-precise machining. In this study, the surface roughness of diamond was improved by thermal diffusion reaction between diamond carbon atoms and ferrous metals at high temperature for diamond thin films deposited by MPCVD.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.95-96
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• 2006

ITO thin film is generally fabricated by various methods such as spray, CVD, evaporation, electron gun deposition, direct current electroplating, high frequency sputtering, and reactive DC sputtering. However, some problems such as peaks, bumps, large particles, and pin-holes on the surface of ITO thin film were reported, which caused the destruction of color quality, the reduction of device life time, and short-circuit. Chemical mechanical polishing (CMP) process is one of the suitable solutions which could solve the problems.

• 한국결정성장학회지
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• 제26권4호
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• pp.131-134
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• 2016

Czochralski 법으로 성장한 RE : YAG ($RE=Nd^{3+}\;,Er^{3+}\;,Yb^{3+}$) 단결정의 표면 결함을 측정하는 chemical polishing 및 etching 조건에 대하여 조사하였다. 최적의 chemical polishing 조건은 시편을 수직 방향으로 고정하고 85 % $H_3PO_4$ 용액에서 $330^{\circ}C$, 30분 동안 진행한 것이었다. 또한 최적의 chemical etching 조건은 85 % $H_3PO_4$ 용액에서 $260^{\circ}C$, 1시간 동안 진행한 것이었고, (111) 면에 $70~80{\mu}m$ 크기의 삼각형 etch pit들이 관찰되었다. 결함 밀도 분석 결과, Nd(1 %) : YAG는 $1.9{\times}10^3$개/$cm^2$, Er(7.3 %) : YAG는 $4.3{\times}10^2$개/$cm^2$, Yb(15 %) : YAG는 $5.1{\times}10^2$개/$cm^2$로 측정되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.15-20
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• 2007

Conditioner wear, copper polish rates, pad temperature and coefficient of friction (COF) are measured for two novel Mitsubishi Materials Corporation designs during an extended wear and polishing test. Both designs are coated with a $Teflon^{TM}$ film to reduce substrate wear and chemical attack. Using optical interferometry, changes in the coating that result in gradual changes in diamond exposure are measured. Theories of the COF, conditioning, and polishing are applied to explain the observed performance differences between the designs.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.1068-1071
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• 2001

Recently, the minimum line width shows a tendancy to decrease and the multi-level to increase in semiconductor. Therefore, a planarization technique is needed, which chemical polishing(CMP) is considered as one of the most important process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as microscratches, abrasive contaminations, and non-uniformity of polished wafer edges. Spin Etching can improve the defects of CMP. It uses abrasive-free chemical solution instead of slurry. Wafer rotates and chemical solution is simultaneously dispensed on a whole surface of the wafer. Thereby chemical reaction is occurred on the surface of wafer, material is removed. On this study, TEOS film is removed by CMP and Spin Etching, the results are estimated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU).

• 한국전기전자재료학회논문지
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• 제16권6호
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• pp.465-470
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• 2003

The chemical mechanical polishing (CMP) process has been widely used for the global planarization of multi-layer structures in semiconductor manufacturing. The CMP process can be optimized by several parameters such as equipment, consumables (pad, backing film and slurry), process variables and post-CMP cleaning. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, the slurry dominates more than 40 %. In this paper, we have studied the CMP characteristics of diluted silica slurry by adding of raw alumina abrasives and annealed alumina abrasives. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.

• 대한기계학회논문집A
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• 제28권1호
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• pp.85-91
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• 2004

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum of 89 arcsec. The surfaces of sapphire wafer were mechanically affected by residual stress during the polishing process. The wave pattern of optical interference of sapphire wafer implies higher abrasion rate in the edge of the wafer than its center from the Newton's ring.