• Proceedings of the KIPE Conference
• /
• 2013.07a
• /
• pp.226-227
• /
• 2013

본 논문에서는 기존의 하이브리드 PLL(Phase Locked Loop) 방법에서 개선된 PLL 방법을 제시한다. 기존의 하이브리드 PLL 방법은 정상분을 동기 좌표계에서 추출하여 다시 정지 좌표계로 변환 후 제어루프를 거쳐 위상을 검출 하는 방법이다. 이를 개선하여 정지 좌표계에서 정상분을 추출하여 제어루프를 거쳐 위상을 검출 하여 기존의 하이브리드 PLL 방법에서 보다 연산 및 제어가 간소해지는 장점이 있다. 제안된 방법을 시물레이션(MATLAB Simulink)을 통해 검증하였다.

• Proceedings of the KIPE Conference
• /
• 2013.07a
• /
• pp.47-48
• /
• 2013

In order to evaluate the response of the grid-connected systems, Phase lock technology is widely used in power electronic devices to obtain the phase angle, amplitude, and frequency of the grid voltage because phase locked loop (PLL) algorithms are very important for grid synchronization and monitoring in the grid connected power electronic devices. This paper presents a performance evaluation in tracking grid angular frequency through single phase synchronization techniques which are an enhanced PLL (EPLL), second-order generalized integrator-PLL (SOGI-PLL), and second-order generalized integrator-frequency locked loop (SOGI-FLL). These techniques are properly analyzed through several steps to get the best technique which can track the frequency accurately and smoothly.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.5 no.3
• /
• pp.215-220
• /
• 2000

본 논문에서는 SRM운전에서 맥동토오크와 부하토오크의 변화로 인한 속도변경을 줄이기 위해 동적 도통각 제어 원리를 이용한 PLL(Phase Locked Loop) 속도제어 방식을 채택하였다. SRM은 많은 장점을 가지고 있으나 토오크리플에 따른 속도변동으로 정밀한 속도제어에 어려움이 있다. SRM 구동 시스템에 PLL을 적용한 결과 전동기는 강인한 정속도 운전을 할 수 있으며, 또한 운전속도에 따라 선행각을 조정함으로서 고효율 구동을 할 수 있었다. 구성된 시스템은 운전속도와 부하의 변화에 따라 선행각이 증가함으로써 뛰어난 동적 속도제어 특성을 갖고 있으며, 인버터 인가전압을 제어하는 선행각을 조정함으로서 일정부하 영역에서 높은 효율특성을 가진다. SRM 구동 시스템의 PLL 속도제어와 고효율 구동을 위한 도통각제어를 위해 TMS320F240 DSP를 사용함으로서 디지털 제어기의 유연성과 소형화를 꾀하였다.

• Journal of Multimedia Information System
• /
• v.5 no.2
• /
• pp.139-142
• /
• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.3
• /
• pp.355-362
• /
• 2003

In this paper, we analyzed the DS/CDMA System with Hybrid SC/MRC diversity, as a method to achieve a good performance by reducing the complexity of system, when PLL gain value was revised a phase gulf among branches to make perfect coherent receive signal. The channel is a multipath Nakagami-m fading channel, we consider user(K), processor gain(N), number of paths(Lp) in DS/CDMA system with hybrid SC/MRC diversity. We found that PLL gain values exist to make perfect coherent receive signal. We verified that DS/CDMA system with Hybrid SC/MRC diversity can improve performance when the proper PLL gain values is used in the system. As a result, we verified that the upper limit of PLL gain value is 5dB to make perfect coherent receive signal in the DS/CDMA system with hybrid SC/MRC diversity.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.12 no.5
• /
• pp.1-9
• /
• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of IKEEE
• /
• v.9 no.1 s.16
• /
• pp.40-46
• /
• 2005

A process variation compensation method called 'regulated drain detection' is proposed. This paper also shows the how this newly invented method is applied to a typical differential PLL. The proposed RDD(regulated drain detection) and its PLL application has been designed and tested in a $0.18{\mu}m$ 1-poly 3-metal plain digital process so that its stable performance and higher yield can be proven. The implemented PLL aimed to the operation range of 80MHz - 240MHz and the total die size is only $0.18{\mu}m$ including the internal loop filter. The tracking jitter characteristics is measured to less than 150 peak-to-peak under l.8V supply rail.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.1
• /
• pp.235-244
• /
• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Journal of Power Electronics
• /
• v.11 no.3
• /
• pp.360-368
• /
• 2011

This paper proposes an active frequency with a positive feedback in the d-q frame anti-islanding method suitable for a robust phase-locked loop (PLL) algorithm using the FFT concept. In general, PLL algorithms for grid-connected PV PCS use d-q transformation and controllers to make zero an imaginary part of the transformed voltage vector. In a real grid system, the grid voltage is not ideal. It may be unbalanced, noisy and have many harmonics. For these reasons, the d-q transformed components do not have a pure DC component. The controller tuning of a PLL algorithm is difficult. The proposed PLL algorithm using the FFT concept can use the strong noise cancelation characteristics of a FFT algorithm without a PI controller. Therefore, the proposed PLL algorithm has no gain-tuning of a PI controller, and it is hardly influenced by voltage drops, phase step changes and harmonics. Islanding prediction is a necessary feature of inverter-based photovoltaic (PV) systems in order to meet the stringent standard requirements for interconnection with an electrical grid. Both passive and active anti-islanding methods exist. Typically, active methods modify a given parameter, which also affects the shape and quality of the grid injected current. In this paper, the active anti-islanding algorithm for a grid-connected PV PCS uses positive feedback control in the d-q frame. The proposed PLL and anti-islanding algorithm are implemented for a 250kW PV PCS. This system has four DC/DC converters each with a 25kW power rating. This is only one-third of the total system power. The experimental results show that the proposed PLL, anti-islanding method and topology demonstrate good performance in a 250kW PV PCS.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.2
• /
• pp.219-225
• /
• 2007

The frequency and phase angle of utility voltage represent very important information fur applications such as AC/DC converters and Uninterruptible Power Supplies(UPS). In a three-phase system, the utility voltage information can be easily obtained by using a utility voltage vector. However, in the case of a single-phase system. the utility voltage information is much harder to obtain. This paper presents a comparative study of single-phase PLL algorithms using virtual 2-phase strategy. Simulation and experimental results, including operation of the PLL structures introduced in reference papers, are presented to allow a performance comparison of the PLL algorithms.