• Title/Summary/Keyword: Pll

Search Result 952, Processing Time 0.031 seconds

PLL Control Scheme for Robust Driving of SRM Drive (SRM 드라이브의 강인한 운전을 위한 PLL 제어 방식)

  • O, Seok-Gyu;Jeong, Tae-Uk;Park, Han-Ung;An, Jin-U;Hwang, Yeong-Mun
    • The Transactions of the Korean Institute of Electrical Engineers B
    • /
    • v.48 no.9
    • /
    • pp.461-466
    • /
    • 1999
  • The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

  • PDF

Comparison of PLL Algorithms Suitable for the Seamless Transfer Control (무순단 절체 기능에 적합한 PLL 알고리즘 비교)

  • Kim, Kiryong;Lee, Jong-Pil;Kim, Tae-Jin;Yoo, Dong-Wook;Kim, Hee-Je
    • Proceedings of the KIPE Conference
    • /
    • 2017.07a
    • /
    • pp.383-384
    • /
    • 2017
  • 분산 발전에 사용되는 PCS는 계통연계 운전 및 독립 운전을 할 수 있어야 한다. 운전 모드 전환 시 발생하는 과도 상태를 최소화하기 위해 무순단 절체 기능이 필요하다. 이 기능을 위해서 계통 이상 유무에 대한 검출이 빠르게 이루어져야하기 때문에 PLL 알고리즘이 중요한 역할을 한다. 본 논문에서는 운전 모드 전환 시 무순단 절체 관점에서 PLL 알고리즘들을 시뮬레이션을 통해 비교하고 이를 바탕으로 적절한 PLL 알고리즘에 대해 고찰한다.

  • PDF

PLL Algorithm Under Unbalanced and Distorted Gird Voltage Conditions (불평형 및 왜곡된 계통 전압 조건에서의 PLL 알고리즘)

  • Lee, C.R.;Chun, T.W.;Lee, H.H.;Kim, H.G.;Nho, E.C.
    • Proceedings of the KIPE Conference
    • /
    • 2014.07a
    • /
    • pp.136-137
    • /
    • 2014
  • 본 논문에서는 계통 전압이 불평형 및 왜곡되었을 경우에 정확한 위상각을 검출 할 수 있는 DSOGI-QSG(dual second order generalized integrator quadrature signal generation)를 이용한 PLL (phase locked loop) 방법을 제안한다. 제안된 PLL 방법은 기존의 DSOGI-PLL 방법과 비교하기 위해, 전압에 불평형 및 왜곡 사고 발생 시 동기각을 검출하는 시뮬레이션을 하였고, 이를 통해 THD가 개선됨을 입증하였다.

  • PDF

A Design Guide to Type-3 PLLs for FMCW Radars (FMCW 레이더용 타입-3 PLL의 설계 가이드)

  • Hwang, In-Duk;Kim, Chang-Hwan
    • The Journal of The Korea Institute of Intelligent Transport Systems
    • /
    • v.11 no.4
    • /
    • pp.70-79
    • /
    • 2012
  • A design guide to type-3 PLLs for FMCW radars is provided. To do that, the cross-over frequencies of the open-loop transfer functions were normalized to 1 Hz and closed-loop properties were compared through simulations using Pspice. As a result, several guides to design type-3 PLLs were provided: 1) secure 45 degrees of phase margin, 2) locate two zeroes at an identical frequency, and 3) poles may be added to raise order of the PLL at higher frequencies than the cross-over frequency of the open-loop transfer function about ten times.

Analysis of PLL Dynamic Characteristics according to Zero Voltage Conditions of Single-phase Grid-connected Inverter (단상 계통연계형 인버터의 영 전압 사고 위상에 따른 PLL 동적 특성 분석)

  • Lee, Taeil;Lee, Kyungsoo
    • Proceedings of the KIPE Conference
    • /
    • 2019.07a
    • /
    • pp.80-82
    • /
    • 2019
  • 태양광발전과 풍력발전으로 대표되는 분산형 전원이 계통에 연계됨에 따라 계통 사고 발생 시에 계통연계형 인버터에 대한 각국의 계통 규정(Grid code)이 더욱 엄격해 지고 있다. 최근 국외 계통 규정에서는 저 전압 사고뿐만 아니라 영 전압 사고 시에 인버터가 일정 시간 계통 연계를 유지하며 무효전류 출력 기법을 통해 계통 복구를 지원할 것을 요구하고 있다. 계통 사고 시, 사고 전압 잔존량에 따라 무효전류를 정확하게 출력하기 위해 인버터의 PLL(Phase Locked Loop) 제어는 중요하다. 그러나 이러한 PLL 제어의 동적 특성은 계통 사고 순간의 전압 강하 및 사고 위상에 따라 영향을 받게 되고 영 전압 사고에서는 위상 추종이 불가능하기 때문에 복합적인 문제가 나타난다. 본 논문에서는 영 전압 사고에서 사고 위상에 따라 각각 다르게 나타나는 PLL 동적 특성을 시뮬레이션을 통해 분석하였다.

  • PDF

A Study on Power Grid PLL Controller Design Using Band Pass Filter (Band Pass Filter 를 활용한 전력 계통 PLL 제어기 설계에 관한 연구)

  • Moon Soo Kim;Byoung Kuk Lee
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2024.05a
    • /
    • pp.455-456
    • /
    • 2024
  • 전력 계통의 Phase 를 제어하기 위해 산업에서 PLL(Phase Locked Loop)제어 시스템을 많이 사용한다. Phase 를 계산함에 있어 계통 전압에 왜곡 발생 시 PLL 을 통한 Phase 에 Noise 가 발생한다. 이를 줄이기 위해, 즉 특정 주파수 대역을 관찰하기 위해 BPF(Band Pass Filter)를 적용하여 PLL 제어기를 설계한 후, Filter 를 적용했을 때와 아닐 때의 위상 차 및 Noise 차이를 분석하여 어떤 경우가 성능적으로 우수한지 확인한다.

Interaction between Poly(L-lysine) and Poly(N-isopropyl acrylamide-co-acrylic acid) in Aqueous Solution

  • Sung, Yong-Kiel;Yoo, Mi-Kyong;Cho, Chong-Su
    • Macromolecular Research
    • /
    • v.8 no.1
    • /
    • pp.26-33
    • /
    • 2000
  • A series of pH/temperature sensitive polymers were synthesized by copolymerizing N-isopro-pyl acrylamide(NIPAAm) and acrylic acid(AAc) . The influence of polyelectrolyte between poly(allyl amine) (PAA) and poly(L-lysine)(PLL) on the lower critical solution temperature(LCST) of pH/temperature sensitive polymer was compared in the range of pH 2∼12. The LCST of PNIPAAm/water in aqueous poly(NIPAAm-co-AAc) solution was determined by cloud point measurements. A polyelectrolyte complex was prepared by mixing poly(NIPAAm-co-AAc) with poly(allyl amine) (PAA) or poly(L-lysine) (PLL) solutions as anionic and cationic polyelectrolytes, respectively. The effect of polyelectrolyte complex formation on the conformation of PLL was studied as a function of temperature by means of circular dichroism(CD). The cloud points of PNIPAAm in the aqueous copolymers solutions were stongly affected by pH, the presence of polyelectrolyte solute, AAc content, and charge density. The polyelectrolyte complex was formed at neutral condition. The influence of more hydrophobic PLL as a polyelectrolyte on the cloud point of PNIPAAm in the aqueous copolymer solution was stronger than that of poly(allyl amine)(PAA). Although polymer-polymer complex was formed between poly(NIPAAm-co-AAc) and PLL, the conformational change of PLL did not occur due to steric hinderance of bulky N-isopropyl groups of PNIPAAm.

  • PDF

Non-cytoxic Effects of Cationic Polyamines on Cultured Hamster Tracheal Surface Epithelial (HTSE) Cells (일차배양 햄스터 기관표면 상피세포에 대한 양이온성 폴리아민의 무독성 효과)

  • 이충재;고광호
    • Biomolecules & Therapeutics
    • /
    • v.6 no.1
    • /
    • pp.14-19
    • /
    • 1998
  • In the present study, we intended to investigate whether cationic polyamines including poly-L-Iysine (PLL) and poly-L-arginine (PLA) induce cytotoxicities to cultured hamster tracheal surface epithelial (HTSE) cells. Confluent HTSE cells were chased for 30 min in the presence of PLL or PLA of different molecular weights. Possible cytotoxicities of PLL or PLA were assessed by measuring both Lactate Dehy- drogenase (LDH) release during treatment and the number of floating cells after treatment and by checking the possible changes on the morphology of HTSE cells during treatment. The results were as follows: in the case of treatment of PLL or rLA of which molecular weight is about 78,000 and 92,000, respectively, (1) there was significant release of LDH during treatment, (2) the number of floating cells were significantly increased after treatment and (3) there were significant changes on the morphology of cultured HTSE cells. However, in the case of PLL or PLA of which molecular weight is under 10,000 (about 9,600 and 8,900, respectively), no significant signs of cytotoxicities mentioned above were detected. We found that cationic polyamines might be non-toxic under specific range of molecular weights and suggest that the cytotoxicity of cationic polyamine might depend on the molecular sizes of each cationic polyamine.

  • PDF

A Fractional-N PLL with Phase Difference-to-Voltage Converter (위상차 전압 변환기를 이용한 Fractional-N 위상고정루프)

  • Lee, Sang-Ki;Choi, Young-Shig
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.12
    • /
    • pp.2716-2724
    • /
    • 2012
  • In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation

  • Kim, Kyung-Ki;Kim, Yong-Bin
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.7 no.1
    • /
    • pp.11-19
    • /
    • 2007
  • This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.