• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.2
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• pp.128-131
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• 2004

In this study Bosch etching process repeating etch and deposition by STS-ICP ASEHR was evaluated. Fundamentally etch depth changes were affected by thickness of deposited PR, $SiO_2$ and depth, and pattern size on the substrate. However etch rates were observed to be changed by variable parameters such as platen power, coil power, and process pressure. Etch rate showed $1.2\mu{m}/min$ and sidewall profile showed $90\pm0.2^\circ$ with platen power 12W, coil power 500W, and etch/passivation cycle 6/7sec. It was confirmed that this result was very typical to Bosch process utilizing ICP.

• Journal of the Korean Vacuum Society
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• v.15 no.6
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• pp.630-636
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• 2006

Scale down of semiconductor gate pattern will make progress centrally line width into transistor according to the high integration and high density of flash memory semiconductor. Recently, the many researchers are in the process of developing research for using the ONO(oxide-nitride-oxide) technology for the gate pattern give body to line breadth of less 100 nm. Therefore, etch rate and etch profile of the line width detail of less 100 nm affect important factor in a semiconductor process. In case of increasing of the platen power up to 50 W at the ICP etcher, etch rate and PR selectivity showed good result when the platen power of ICP etcher has 100 W. Also, in case of changing of HBr gas flux at the platen power of 100 W, etch rate was decreasing and PR selectivity is increasing. We founded terms that have etch rate 320 nm/min, PR selectivity 3.5:1 and etch slope have vertical in the case of giving the platen power 100 W and HBr gas 35 sccm at the ICP etcher. Also notch was not formed.

• Clean Technology
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• v.9 no.3
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• pp.101-105
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• 2003

Plasma etching technology has been developed since it is recognized that silicon etching is very crucial in MEMS(Micro Electro Mechanical System) technology. In this study ICP(Inductive Coupled Plasma) technology was used as a new plasma etching to increase ion density without increasing ion energy, and to maintain the etching directions. This plasma etching can be used for many MEMS applications, but it has been used for PCR(Polymerase Chain Reaction) device fabrication. Platen power, Coil power and process pressure were parameters for observing the etching rate changes. Conclusively Platen power 12W, Coil power 500W, etchng/passivation cycle 6/7sec gives the etching rate of $1.2{\mu}m/min$ and sidewall profile of $90{\pm}0.7^{\circ}$, exclusively. It was concluded from this study that it was possible to minimize the environmental effect by optimizing the etching process using SF6 gas.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05e
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• pp.77-80
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• 2003

MEMS(Micro Electro Mechanical System) 기술에서 실리콘 식각기술의 중요성으로 플라즈마 식각기술의 개발이 꾸준히 진행되고 있다. 이중에서 ICP(Inductive Coupled Plasma)는 기존의 증착장치에 유도결합식 플라즈마를 추가로 발생시켜 증착막의 특성을 획기적으로 개선시키는 가장 최근에 개발된 기술이며, 이용에너지를 증가시키지 않고도 이용밀도를 높이고 이용업자들에 방향성을 가할 수 있는 새로운 플라즈마 기술로, 주로 MEMS 제조공정에 응용되고 있다. 본 연구에서는 STS-ICP $ASE^{HR}$을 이용하여 식각과 증착공정을 반복하여 식각을 하는 Bosch 식각에 관하여 연구하였다 STS-ICP $ASE^{HR}$ 장비의 Platen power, Coil power 및 Process pressure에 다양한 변화를 주어 각 변수에 따른 식각속도를 관찰하였다. 각 공정별 변수를 변화시킨 결과 Platen power 12W, Coil power 500W, 식각/Passivation Cycle 6/7sec 일 경우 식각속도는 $1.2{\mu}m$/min 이었고, Sidewall profile은 $90{\pm}0.7^{\circ}$로 나타나 매우 우수한 결과를 보였다.

• Journal of Sensor Science and Technology
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• v.24 no.1
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.244-250
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• 2008

An inductively coupled plasma etching process to replace an existing slower rate reactive ion etching process for $60{\mu}m$ diameter via-holes using Cl2/BCl3 gases has been investigated. Process pressure and platen power were varied at a constant ICP coil power to reproduce the RIE etched $200{\mu}m$ deep via profile, at high etch rate. Desired etch profile was obtained at 40 m Torr pressure, 950 W coil power, 90W platen power with an etch rate ${\sim}4{\mu}m$/min and via etch yield >90% over a 3-inch wafer, using $24{\mu}m$ thick photoresist mask. The etch uniformity and reproducibility obtained for the process were better than 4%. The metallized via-hole dc resistance measured was ${\sim}0.5{\Omega}$ and via inductance value measured was $\sim$83 pH.

• Journal of the Korean Ceramic Society
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• v.39 no.6
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• pp.570-575
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• 2002

The present tendency of electrical and electronics is concentrated on MEMS devices for advantage of miniaturization, intergration, low electric power and low cost. Therefore it is essential that high aspect ratio and high etch rate by HDP technology development, so that silicon deep trench etching reactions was studied by ICP equipment. Deep trench etching of silicon was investigated as function of platen power, etch step time of etch/passivation cycle time and SF$\_$6/:C$_4$F$\_$8/ flow rate. Their effects on etch profile, scallops, etch rate, uniformity and selectivity were also studied.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.16 no.1
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• pp.65-73
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• 2020

Integrity evaluations on a platen superheater were conducted as per ASME Section VIII Division 2(hereafter 'ASME VIII(2)') which was originally used for design with implicit consideration of creep effects. A platen superheater subjected to severe loading conditions of high pressure and high temperature at creep regime in a supercritical thermal plant in Korea was chosen for present study. Additional evaluations were conducted as per nuclear-grade high-temperature design rule of RCC-MRx that takes creep effects into account explicitly. Comparisons of the two results from ASME VIII(2) and RCC-MRx were conducted to quantify the conservatism of ASME VIII(2). From present analyses, it was shown that the design evaluation results exceeded allowable limits of RCC-MRx for the plant design conditions although limits of ASME VIII(2) were satisfied regardless of operation time, which means that design as per ASME VIII(2) might be potentially non-conservative in case of operation in creep range. A high-temperature design evaluation program as per RCC-MRx, called 'HITEP_RCC-MRx' has been used and it was shown that pressure boundary components can be designed reliably with the program especially for the loading conditions of long-term creep conditions.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.1 s.256
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• pp.50-54
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• 2007

Nickel nano and microstructures are fabricated with simple process. The fabrication process consists of nickel deposition, lithography, nickel ion etching and plasma ashing. Well-aligned nickel nanowalls and nickel self-encapsulated microchannels were fabricated. We found that the ion etching condition as a key fabrication process of nickel nanowalls and self-encapsulated microchannels, i.e., 40 sccm Ar flow, 550 W RF power, 15 mTorr working pressure, and $20^{\circ}C$ water cooled platen without using He backside cooling unit and with using it, respectively. We present the experimental results and discuss the formational conditions and the effect of nickel redeposition on the fabrication of nickel nano and microstructures.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.423-430
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• 2011

Multi-input multi-output (MIMO) dynamic matrix control (DMC) technique is applied to control steam temperatures in a large-scale ultrasupercritical once-through boiler-turbine system. Specifically, four output variables (i.e., outlet temperatures of platen superheater, finish superheater, primary reheater, and finish reheater) are controlled using four input variables (i.e., two spray valves, bypass valve, and damper). The step-response matrix for the MIMO DMC is constructed using the four input and the four output variables. Online optimization is performed for the MIMO DMC using the model predictive control technique. The MIMO DMC controller is implemented in a full-scope power plant simulator with satisfactory performance.