• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.109-114
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• 2004

This paper proposes an advanced circuit for the fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling of each sensor pixel. The fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2003.09a
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• pp.45-45
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• 2003

The aim of this study was the characterization and performance validation of new prototype avalanche photodiode (APD) arrays for positron emission tomography (PET). Two different APD array prototypes (noted A and B) developed by Radiation Monitoring Device (RMD) have been investigated. Principal characteristics of the two APD array were measured and compared. In order to characterize and evaluate the APD performance, capacitance, doping concentration, quantum efficiency, gain and dark current were measured. The doping concentration that shows the impurity distribution within an APD pixel as a function of depth was derived from the relationship between capacitance and bias voltage. Quantum efficiency was measured using a mercury vapor light source and a monochromator used to select a wavelength within the range of 300 to 700 nm. Quantum efficiency measurements were done at 500 V, for which the APD gain is equal to one. For the gain measurements, a pencil beam with 450 nm in wavelength was illuminating the center of each pixel. The APD dark currents were measured as a function of gain and bias. A linear fitting method was used to determine the value of surface and bulk leakage currents. Mean quantum efficiencies measured at 400 and 450 nm were 0.41 and 0.54, for array A, and 0.50 and 0.65 for array B. Mean gain at a bias voltage of 1700 V, was 617.6 for array A and 515.7 for type B. The values based on linear fitting were 0.08${\pm}$0.02 nA 38.40${\pm}$6.26 nA, 0.08${\pm}$0.0l nA 36.87${\pm}$5.19 nA, and 0.05${\pm}$0.00 nA, 21.80${\pm}$1.30 nA in bulk surface leakage current for array A and B respectively. Results of characterization demonstrate the importance of performance measurement validating the capability of APD array as the detector for PET imaging.

• Journal of Radiation Industry
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• v.6 no.1
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

• Journal of the Korean Society of Radiology
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• v.17 no.3
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• pp.359-365
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• 2023

In order to satisfy the requirements of dynamic X-ray imaging with high frame rate and low image lag, minimizing parasitic capacitance in photodiode and overlapped electrodes in pixels is critically required. This study presents duoPIX^TM dynamic X-ray imaging sensor composing of readout thin film transistor, reset thin film transistor and photodiode in a pixel. Furthermore, dynamic X-ray detector using duoPIX^TM imaging sensor was manufactured and evaluated its X-ray imaging performances such as frame rate, sensitivity, noise, MTF and image lag. duoPIX^TM dynamic X-ray detector has 150 × 150 mm² imaging area, 73 um pixel pitch, 2048 × 2048 matrix resolution(4.2M pixels) and maximum 50 frames per second. By means of comparison with conventional dynamic X-ray detector, duoPIX^TM dynamic X-ray detector showed overall better performances than conventional dynamic X-ray detector as shown in the previous study.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.733-738
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• 2006

As the film transistor-liquid crystal display (TFTLCD) panels become larger and provide higher resolution, the propagation delay of row and column lines, the voltage modulation of Vcom, and the response time of liquid crystal affect the display images now more than in the past. It is more important to understand the electrical characteristic of TFT-LCD panels these days. This paper describes the electrical model of a 15-inch XGA ($1024{\times}768$) TFT-LCD panel. The parasitic resistance and capacitance of its panel are obtained by 3D simulation of a sub pixel. The accuracy of these data is verified by the measured values in an actual panel [1]. The developed panel simulation platform, the equivalent circuit of a 15-inch XGA panel, is simulated by HSPICE. The results of simulation are compared with those of experiment, according to changing the width of signal. Especially, the proposed simulation platform for modeling TFTLCD panels can be applied to large size LCD TVs. It can help panel and circuit designers to verify their ideas without making actual panels and circuits.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.515-518
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• 2005

In this paper, we report on our theoretical study on the effect of surface anchoring. Molecular dynamics as well as optical characteristics of PVA cell are computer-simulated with 3D-FEM numerical solver, TechWiz $LCD^{(R)}$. Although simulation parameters are the same except for the consideration of surface anchoring, the simulation reveals that optical transmittance is improved by more than 8% for the weak anchoring case with comparison to the strong anchoring case. Moreover, capacitance between pixel and common electrode is 7% lower for the strong anchoring than that for the weak anchoring. This implies that there exists an appreciable difference between the strong anchoring case and the weak anchoring case. It is very important to take the effect of surface anchoring into account in order to figure out the optical characteristics of an LCD cell more accurately.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.80-86
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• 2014

A low-noise readout circuit is studied for 2-D capacitive microbolometer focal plane arrays (FPAs). In spite of the merits of the integration method, a simple and effective pixelwise readout circuit without integration is used for input circuit because of a small pixel size and narrow noise bandwidth. To reduce the power consumption and the kT/C noise, which is the dominant noise of the capacitive microbolometer FPAs with small capacitance, a new correlated double sampling (CDS) is used for columnwise circuit. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed circuit effectively reduces the kT/C noise and the other low-frequency noise of microbolometer, and the noise characteristics of the fabricated chip have been verified by measurements. The rms noise voltage of the proposed circuit is reduced from 30 % to 55 % compared to that of the simple readout input circuit, and the noise equivalent temperature difference (NETD) of the proposed circuit is very low value of 21.5 mK.