• Journal of Sensor Science and Technology
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• v.26 no.2
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• pp.85-90
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• 2017

A wide dynamic range (WDR) CMOS image sensor (CIS) was developed with a specialized readout architecture for realizing high-sensitivity (HS) and low-sensitivity (LS) reading modes. The proposed pixel is basically a three-transistor (3T) active pixel sensor (APS) structure with an additional transistor. In the developed WDR CIS, only one mode between the HS mode for relatively weak light intensity and the LS mode for the strong light intensity is activated by an external controlling signal, and then the selected signal is read through each column-parallel readout circuit. The LS mode is implemented with the column capacitors and a feedback structure for adjusting column capacitor size. In particular, the feedback circuit makes it possible to change the column node capacitance automatically by using the incident light intensity. As a result, the proposed CIS achieved a wide dynamic range of 94 dB by synthesizing output signals from both modes. The prototype CIS is implemented with $0.18-{\mu}m$ 1-poly 6-metal (1P6M) standard CMOS technology, and the number of effective pixels is 176 (H) ${\times}$ 144 (V).

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.793-799
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• 2016

A multi-purpose sensor interface that provides dual-mode operation of fingerprint sensing and physiological signal detection is presented. The dual-mode sensing capability is achieved by utilizing inter-pixel shielding patterns as capacitive amplifier's input electrodes. A prototype readout circuit including a fingerprint panel for feasibility verification was fabricated in a $0.18{\mu}m$ CMOS process. A single-channel readout circuit was implemented and multiplexed to scan two-dimensional fingerprint pixels, where adaptive calibration capability against pixel-capacitance variations was also implemented. Feasibility of the proposed multi-purpose interface was experimentally verified keeping low-power consumption less than 1.9 mW under a 3.3 V supply.

• Journal of Sensor Science and Technology
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• v.26 no.4
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• pp.223-227
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• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.79-82
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• 2015

This paper proposes a novel complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) and presents its performance characteristics. The proposed APS exhibits a linear-logarithmic response, which is simulated using a standard $0.35-{\mu}m$ CMOS process. To maintain high sensitivity and improve the dynamic range (DR) of the proposed APS at low and high-intensity light, respectively, two additional nMOSFETs are integrated into the structure of the proposed APS, along with a photogate. The applied photogate voltage reduces the sensitivity of the proposed APS in the linear response regime. Thus, the conversion gain of the proposed APS changes from high to low owing to the addition of the capacitance of the photogate to that of the sensing node. Under high-intensity light, the integrated MOSFETs serve as voltage-light dependent active loads and are responsible for logarithmic compression. The DR of the proposed APS can be improved on the basis of the logarithmic response. Furthermore, the reference voltages enable the tuning of the sensitivity of the photodetector, as well as the DR of the APS.

• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.366-370
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• 2022

A 12 ㎛ pixel-sized 360 × 240 microbolometer focal plane array (MBFPA) was fabricated using a complementary metaloxide-semiconductor (CMOS)-compatible process. To release the MBFPA membrane, an amorphous carbon layer (ACL) processed at a low temperature (<400 ℃) was deposited as a sacrificial layer. The thermal time constant of the MBFPA was improved by using serpentine legs and controlling the thickness of the SiNx layers at 110, 130, and 150 nm on the membrane, with response times of 6.13, 6.28, and 7.48 msec, respectively. Boron-doped amorphous Si (a-Si), which exhibits a high-temperature coefficient of resistance (TCR) and CMOS compatibility, was deposited on top of the membrane as an IR absorption layer to provide heat energy transformation. The structural stability of the thin SiNx membrane and serpentine legs was observed using field-emission scanning electron microscopy (FE-SEM). The fabrication yield was evaluated by measuring the resistance of a representative pixel in the array, which was in the range of 0.8-1.2 Mohm (as designed). The yields for SiNx thicknesses of SiNx at 110, 130, and 150 nm were 75, 86, and 86%, respectively.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.131-136
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• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.198-201
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• 2004

We have developed a multi-domain vertically aligned liquid crystal display (MVA-LCD) that produces natural gray-scale images even at high viewing angles. We divided each pixel into two areas and set different threshold voltages for each sub-area. A transparent electrode in a sub-area is not connected directly to the source electrodes but via the capacitance of the SiN layer. In particular, light-orange skin color appears very natural, even at a high inclination angle. The contrast ratio is over 500 in the normal direction and over 10 from any viewing angle.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1111-1114
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• 2006

We have developed a 2 inch LTPS-TFT AMOLED display with a top emission structure on a $50-{\mu}m-thick$ metal foil. The Active matrix back planes were fabricated with the p-channel LTPS TFT with a conventional pixel circuit consisting of 2 transistors and 1 capacitance. The p-channel TFTs on the metal foil exhibited the field-effect mobility of $22cm^2/Vs$. Finally, a images from prototype monochrome AMOLED displays are successfully presented, with $64{\times}88$ pixels and 56-ppi resolution.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.739-742
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• 2003

본 연구에서는 정전계 에너지를 이용하여 IPS-LCD의 화소와 각 전극간 정전용량을 엄정한 방법으로 계산하였다. 정전계 에너지는 전극의 유한한 크기로 인해 발생하는 측면 전장효과를 고려한 3차원 방향자와 전위분포를 시뮬레이션 함으로써 얻을 수 있었다. 수치해석 방법으로는 유한차분법을 사용하였다. 그 결과 IPS-LCD의 화소 정전용량과 게이트-공통전극간 정전용량은 구조적 특성으로 인해 기존의 TN-LCD와 비교하여 1/16배 가량으로 훨씬 더 작은 값을 나타냄이 확인되었다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1374-1382
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• 1995

In TFT-LCDs, as the display size area becomes larger, and the resolution higher, we have to consider the image degradation effects due to the incorporation of the TFT-LCD parameters such as the data-line resistance, the common electrode resistance, the data-line to common parasitic capacitance, and the output characteristics of driver ICs. One of the degradation effects is crosstalk resulting from the coupling between the source bus-line and common electrode. Since a source signal which represents a large number of display data is supposed to vary frequently, the common signal level is affected through the coupling effect, resulting in the degradation of nearby pixel drive signals. Therefore, we proposed a method to compensate for this source-common electrode coupling effect, we also designed and experimented the feasibility of our crosstalk compensation circuit in the actual TFT-LCD. We saw that the newly designed compensation circuit greatly reduced the crosstalk in display pattern image.