• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.613-616
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• 1999

An active-matrix LCD using thin film transistors (TFTs)has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed, The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1750-1752
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• 1999

An active-matrix liquid crystal display (LCD) using thin film transistors (TFTs) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the sate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed. The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 춘계종합학술대회
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• pp.249-252
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• 2003

본 논문에서는 반도체 방식의 직접 터치식 capacitive type 지문인식센서의 신호처리를 위한 회로를 제안하였다. 센서로부터의 capacitance의 변화를 전압의 신호로 전환하기 위해서 charge-sharing 방식의 회로를 적용하였다. 지문센서 감도저하의 가장 큰 원인인 sensor plate에 존재하는 parasitic capacitance를 제거하여 ridge와 valley 사이의 전압차를 향상시키기 위하여 기존과는 다른 아날로그 버퍼회로를 설계 적용하였다. 센서 하부회로와의 isolation 대책을 통하여 ESD 및 노이즈방지를 위한 설계를 실시하였다. 제안된 신호처리회로는 128$\times$144 pixel 규모의 회로로 구현되었다. 본 설계회로는 향후 생체인식을 이용한 정보보호용 지문인식 시스템에 응용될 수 있으리라 본다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.71-72
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• 2000

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the mutual coupling capacitances present in a pixel. The mutual coupling capacitance causes a pixel voltage error. In this study, semi-empirical model, which is adopted from VLSI interconnection capacitance calculations, is used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and arbitrary given image pattern, the root mean square (RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained this study can be utilized to design the larger area and finer image quality panel.

• 한국전기전자재료학회논문지
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• 제20권3호
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• pp.250-256
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• 2007

We analyzed the effect of a pixel and all the inter-electrode capacitances in a unit pixel of TFT-LCDs on the gray scale capability. The pixel and all the inter-electrode parasitic capacitances were obtained from the tree dimensional profiles of potential distribution and molecular director considering lateral fields generated at the edge of the pixel. To obtain the RMS and kickback voltages of the pixel, we constructed an equivalent circuit of the panel containing all the parasitic capacitances. The calculation was performed though H-SPICE. As results, we confirmed that the pixel becomes smaller, the effect of parasitic capacitances on the gray scale capability becomes larger.

• 한국정보통신학회논문지
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• 제7권6호
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• pp.1297-1303
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• 2003

반도체 방식의 capacitive type 지문인식센서의 신호처리를 위한 개선된 회로를 설계하였다. 최 상위 sensor plate가 지문의 굴곡을 감지한 capacitance의 변화를 전압의 신호로 전환하기위해서 charge-sharing 방식의 회로를 적용하였다. 지문센서 감도저하의 가장 큰 원인인 sensor plate에 존재하는 parasitic capacitance를 최소화하고 ridge와 valley 사이의 전압차를 향상시키기 위하여 기존과는 다른 아날로그버퍼회로를 설계하였다. 센서전압과 기준전압 신호를 비교하기 위해서 비교기를 설계하였으며, 센서어레이의 수직, 수평간 isolation 대책을 통하여 ESD 및 노이즈방지를 위한 설계를 제안하였다. 제안된 신호처리회로는 128${\times}$l44 pixel 규모의 회로로 구현되었다. 본 설계회로는 향후 생체인식을 이용한 정보보호용 지문인식 시스템에 응용될 수 있으리라본다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.208-210
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• 2008

We have developed a LCD Panel that form storage capacitance for pixels between pixel electrode of bottom glass and common electrode of top glass. This method could make higher transmission and higher production yield than before by removing storage electrode line and capacitance on the bottom glass by simplifying bottom pixel structure.

• ETRI Journal
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• 제34권4호
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• pp.633-636
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• 2012

A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.557-560
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• 1999

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the parasitic capacitive elements present in a pixel. The capacitive coupling of the data line signal onto the pixel causes a pixel voltage error. In this study semi-empirical capacitance model which is adopted from VLSI interconnection capacitance calculations was used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and given image pattern, the root mean square(RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.356-359
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• 2007

Writable Cholesteric Liquid Crystal Display and the algorithm used to detect its image were developed. We could use any hard tip, ex: the tip of a forefinger, to directly write an image on the surface of Cholesteric Liquid Crystal Display (CHLCD). By measuring the capacitance of one pixel of test cell (12mm x 15mm/1x1), F-state or P-state could be detected. By measuring the capacitance of one pixel of 4.1" CHLCD (241um x 241um/ 320x320), F-state or Pstate could not be detected, due to the effect of parasitic capacitance. Therefore, high frequency measurement and the algorithm were developed to detect the image on CHLCD.