• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1461-1466
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• 2003

This paper presents the effects of the fin array and pitch on the frost layer growth of a heat exchanger. The numerical results are compared with experimental data of a cold plate to validate the present model, and agree well with experimental data within a maximum error of 8%. The characteristics of the frost formation on staggered fin array are somewhat different from those of in-line array. The frost layer at the first fin of the in-line array grows rapidly, compared to second fin, whereas the difference of the frost layer growth between the fins of the staggered array is small. For fin pitch below 10 mm, the frost layer growth of second fin in the staggered array is affected by that of first fin. The frost layer growth and heat transfer of single fin deteriorate with decreasing fin pitch regardless of fin array, however, the thermal performance of a heat exchanger, considering increase of heat surface area, becomes better.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.15 no.9
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• pp.711-717
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• 2003

This paper presents the effects of the fin array and pitch on the frost layer growth of a heat exchanger. The numerical results are compared with experimental data of a cold plate to validate the present model, and agree well with experimental data within a maximum error of 8%. The frost behaviors of the staggered fin array are somewhat different from those of in-line array. The frost layer formed on the first fin of the in-line array grows rapidly, compared to second fin, whereas the difference of the frost layer growth between the fins of the staggered array is small. For fin pitch below 10 m, the frost layer growth of second fin in the staggered array is affected by that of first fin. The thickness of the frost layer and heat transfer of single fin are reduced with decreasing fin pitch regardless of fin array. However, the thermal performance of a heat exchanger is enhanced due to the increase of heat transfer surface area.

• The KSFM Journal of Fluid Machinery
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• v.16 no.6
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• pp.40-47
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• 2013

In this paper, a numerical study was performed to investigate the performance characteristics of a pre-heater. The effects of fin pitch and fin array type(in-line, staggered, leaned array) were reported in terms of Colburn j-factor and Fanning friction factor f, as a function of Re. Three-dimensional numerical simulation has been performed by using flow analysis program, FLUENT 13.0. The results show that Colburn j-factor decreases with the decrease of fin pitch attached in the annular tube. But the fin pitch has little effect on f-factor. The staggered array and leaned array show improved heat transfer performance compared with in-line array, so that Colburn j-factor was increased. It also shows that the f-factor of leaned array is the highest in the studied range of Reynolds number.

• International Journal of Automotive Technology
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• v.8 no.6
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• pp.753-760
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• 2007

In this paper, a roll and pitch estimation algorithm using a set of accelerometers and wireless sensor networks(S/N) is presented for use in a passenger vehicle. While an inertial measurement unit(IMU) is generally used for roll/pitch estimation, performance may be degraded in the presence of longitudinal acceleration and yaw motion. To compensate for this performance degradation, a new roll and pitch estimation algorithm is proposed that uses an accelerometer array, global positioning system(GPS) and in-vehicle networks to get information from yaw rate and roll rate sensors. Angular acceleration and roll and pitch approximation are first calculated based on vehicle kinematics. A discrete Kalman filter is then applied to estimate both roll and pitch more precisely by reducing noise from the running engine and from road disturbance. Finally, the feasibility of the proposed algorithm is shown by comparing its performance experimentally with that of an IMU in the framework of an indoor test platform as well as a test vehicle.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2009.10a
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• pp.575-577
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• 2009

Traditionally, tire made a role of function, which is supporting vehicle load, making brake, transferring, traction etc. So, there are a lot of studying for the tire. especially, tire noise is one of the most important parameter in the car noise. this thesis shows the method how to reduce the tire noise by using the optimal pitch sequence. Because the optimal pitch sequence prevents tire from generating the pure tone while driving the car on the ground.

• Tunnel and Underground Space
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• v.4 no.3
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• pp.256-260
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• 1994

HLW canister array was designed by FLLSSM program, considering the thermal concentration. Rock properties were chosen as those of granite, the most possible bedrock for the repository in Korea. It was shown that repository area and excavation volumes can be determined by the pitch or distance between canisters. Pitch can be reduced to 0.6 m assuming the tolerance temperature as 200$^{\circ}C$. Thermal concentration was reduced as storage time for cooling the canister passed. After 10 years of storage the thermal problems seemed to be negligible.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.5
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• pp.559-563
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• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start