• The Journal of the Korea Contents Association
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• v.2 no.2
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• pp.47-52
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• 2002

Recently, network overload is greatly increased with explosive use of internet. So the Hyper-Text Transfer Protocol(HTTP) is required improve of performance for decreasing of latency on the web document processing. The P-HTTP is one of the improved mood of He HTTP and has pipeline structure, but performance of the P-HTTP is decreased on interaction between the TCP and P-HTTP. Modification of structural design of the HTTP is not enough to improvement this problem. In this paper, we analyse performance of the HTTP and P-HTTP, and propose a new method on improving HTTP latency for the efficient web document processing.

• Journal of Advanced Research in Ocean Engineering
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• v.2 no.3
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• pp.99-111
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• 2016

Seabed affected by scouring, sedimentation, and siltation occurrences often cause exposure, which induces risks to existing structures or crude oil or gas pipeline buried subsea. In order to prevent possible risks, more economical structure installation methodology is proposed in this study by predicting and managing the risk. Also, the seabed does not only consist of sandy material, but clayey soil is also widespread, and the effect of undrained shear strength should be considered, and by cyclic environmental load, pore water pressure will occur in the seabed, which reduces shear strength and allows particles to move easily. Based on previous research regarding sedimentation or erosion, the average value of external environmental loads should be applied; for scouring, a 100-year period of environmental conditions should be applied. Also, sedimentation and erosion are mainly categorized by the bed load and suspended load; also, they are calculated as the sum of bed load and suspended load, which can be obtained from the movement of particles caused by sedimentation or erosion.

• ETRI Journal
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• v.42 no.3
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• pp.376-387
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• 2020

Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.220-221
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• 2005

Sub-bottom profiler(SBP) has been used extensively for the mapping of basement in the foundation design of offshore structure, for pre- and post-dredging operations within harbors and channels, for selection of pipeline routes, sitting of drilling platforms, and in the exploration for an aggregates such as sands and gravels. During the construction of Siwha embankment for irrigation water and the expansion of arable land, the breaking of an embankment unfortunately occurred so that a lot of riprap was swept away and widely dispersed by the tide and strong current. The feasibility study for the construction of the tidal-powered electric plant in Siwha embankment was performed quite recently. Therefore we made use of SBP survey to investigate the distribution of the lost riprap. We could successfully map out the distribution of the lost riprap from the reflection amplitude characteristics of the sediments in SBP data set. We demonstrated the variation of reflection amplitude versus the sediments with and/or without riprap by means of the numerical modeling of acoustic wave equation using finite difference method. Also we examined an amplitude anomaly of the ripraped area through the physical modeling using ultrasonic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.14 no.2
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• pp.119-127
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• 2004

Butterfly valves are popularly used in service in the industrial and water works pipeline systems with large diameter because of its lightweight, simple structure and the rapidity of its manipulation. Sometimes cavitation can occur. resulting in noise, vibration and rapid deterioration of the valve trim, and do not allow further operation. Thus, the monitoring of cavitation is of economic interest and is very importance in industry. This paper proposes a condition monitoring scheme using statistical feature evaluation and support vector machine (SVM) to detect the cavitation conditions of butterfly valve which used as a flow control valve at the pumping stations. The stationary features of vibration signals are extracted from statistical moments. The SVMs are trained, and then classify normal and cavitation conditions of control valves. The SVMs with the reorganized feature vectors can distinguish the class of the untrained and untested data. The classification validity of this method is examined by various signals that are acquired from butterfly valves in the pumping stations and compared the classification success rate with those of self-organizing feature map neural network.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.255-266
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• 2015

In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.416-424
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• 2014

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.