• 한국정밀공학회지
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• 제23권3호
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• pp.156-162
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• 2006

Direct fabrication of nano patterns has been studied employing a nano-stereolithography (NSL) process. The needs of nano patterning techniques have been intensively increased for diverse applications for nano/micro-devices; micro-fluidic channels, micro-molds. and other novel micro-objects. For fabrication of high-aspect-ratio (HAR) patterns, a thick spin coating of SU-8 process is generally used in the conventional photolithography, however, additional processes such as pre- and post-baking processes and expansive precise photomasks are inevitably required. In this work, direct fabrication of HAR patterns with a high spatial resolution is tried employing two-photon polymerization in the NSL process. The precision and aspect ratio of patterns can be controlled using process parameters of laser power, exposure time, and numerical aperture of objective lens. It is also feasible to control the aspect ratio of patterns by truncation amounts of patterns, and a layer-by-layer piling up technique is attempted to achieve HAR patterns. Through the fabrication of several patterns using the NSL process, the possibility of effective patterning technique fer various N/MEMS applications has been demonstrated.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.186-189
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and room temperature process. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing process. The OTFT array with dielectric layer and organic active semiconductor layer formed at room temperature or at a temperature lower than $40^{\circ}C$. The microcontact printing process using SAM and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even submicron size, and reduced the fabrication process by 10 steps compared with photolithography. Since the process was done in room temperature, there was no pattern shrinkage, transformation, and bending problem appeared. Also, it was possible to improve electric field mobility, to decrease contact resistance, to increase close packing of molecules by SAM, and to reduce threshold voltage by using a big dielectric.

• Korea-Australia Rheology Journal
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• 제14권2호
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• pp.63-70
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• 2002

Chemical mechanical planarization (CMP) is the polishing process enabled by both chemical and mechanical actions. CMP is used in the fabrication process of the integrated circuits to achieve adequate planarity necessary for stringent photolithography depth of focus requirements. And recently copper is preferred in the metallization process because of its low resistivity. We have studied the effects of chemical reaction on the polishing rate and surface planarity in copper CMP by means of numerical simulation solving Navier-Stokes equation and copper diffusion equation. We have performed pore-scale simulation and integrated the results over all the pores underneath the wafer surface to calculate the macroscopic material removal rate. The mechanical abrasion effect was not included in our study and we concentrated our focus on the transport phenomena occurring in a single pore. We have observed the effects of several parameters such as concentration of chemical additives, relative velocity of the wafer, slurry film thickness or ash)tract ratio of the pore on the copper removal rate and the surface planarity. We observed that when the chemical reaction was rate-limiting step, the results of simulation matched well with the experimental data.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 춘계학술대회 논문집
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• pp.503-507
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• 2002

Mask manufacturing is a high COC and COO process in developing of semiconductor devices, because of the mass production tool with high resolution. Direct writing has been thought to be one of the patterning method to cope with development or small-lot production of the device. This study focused on the development of the direct, mastless patterning process using stereolithography tool for the easy and convenient application to micro and miso scale products. Experiments are utilized by three dimensional CAD/CAM as a mask and photo-curable resin as a photo-resist in a conventional stereo-lithography apparatus. Results show that the resolution of the pattern was achieved about 300 micron because of complexity of SLA apparatus settings, inspite of 100 micro of inherent resolution. This paper concludes that photo resist and laser spot diameter should be adjusted to get finer patterns and the proposed method is significantly feasible to mastless and low cost patterning with micro and miso scale.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1249-1252
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• 2007

We have fabricated 3.5” transparent AM-OLED panel driven by PEALD grown ZnO TFT. The performance of ZnO thin film transistor was improved by adapting top gate structure, protection layer for ZnO from photolithography process, optimizing temperature and plasma power of ZnO growth process. The ZnO-TFT has a mobility of $8.9cm^2/V.s$, a subthreshold swing of 0.95V, and an on/off ratio of $10^7$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.66-66
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• 2006

Development of ArF Photo-lithography process has proceeded with the increase of numerical aperature (NA) and the decrease of resist thickness. It makes many problems such as cost and process complexity. A novel spin-on hard mask system is proposed to overcome many problems Spin-on hard mask composed of two layers of siloxane and carbon. The optical thickness of two layers is designed from reflectivity measurement at specified n, k respectively. The property of photo-resist shows different results according to Si contents. Si-contents was measured XPS(X-ray Photoelectron spectroscopy).

• 전자공학회논문지D
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• 제35D권2호
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• pp.60-69
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• 1998

Polysilicon surface mdoification tecnique is developed to reduce the sticking of microstructures fabricated by micromachining. Modified anti-sticking grain holes are simply formed by two-step dry eth without additional photolithography nor deposition of thin films. Both process-induced sticking and in-use sticking are successfully reduced more than two times by adopting grain holed polysilicon substrate. A sticking model for cantilever beam is derived. This model includes bending moment stems from stress gradient along the thickness directionof structural polysilicon. Because the surface tension of rinse liquid and the surface energy of the solids to be stuk tend to decrease in recently developed anti-sticking techniques, the effect of stress gradient will play an important role to analyze the sticking phenomena. Effect of the temperature during post-release rinse and dry is modelled and verified experimentally. Based on developed anti-sticking polysilicon structure and the sticking model, sticking of microstructure, fabricated by simple wet process including sacrificial layer etch and rinse with deionized water without special equimpment for post-release rinse and dry was alleviated more than 3.5 times.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.169-173
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• 2003

We demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon) printed circuit board (PCB). The copper lines were formed with $100\;{\mu}m$ width and $18\;{\mu}m$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of $100-200\;{\mu}m$. The DFRs of $15\;{\mu}m$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100^{\circ}C\;to\;150^{\circ}C$ and laminating speed. We found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63 cm/s. And the smallest size of indium solder bump was diameter of $50\;{\mu}m$ with pitch of $100\;{\mu}m$.

• Transactions on Electrical and Electronic Materials
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• 제18권6호
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• pp.341-344
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• 2017

Infrared (IR) filters were developed to implement integrated three-dimensional (3D) image sensors that are capable of obtaining both color image and depth information at the same time. The combination of light filters applicable to the 3D image sensor is composed of a modified IR cut filter mounted on the objective lens module and on-chip filters such as IR pass filters and color filters. The IR cut filters were fabricated by inorganic $SiO_2/TiO_2$ multilayered thin-film deposition using RF magnetron sputtering. On-chip IR pass filters were synthetized by dissolving various pigments and dyes in organic solvents and by subsequent patterning with photolithography. The fabrication process of the filters is fairly compatible with the complementary metal oxide semiconductor (CMOS) process. Thus, the IR cut filter and IR pass filter combined with conventional color filters are considered successfully applicable to 3D image sensors.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.441-441
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• 2014

The characteristics of hybrid conductive films based on multilayer graphene and silver grid have been investigated for the high-performance and flexible organic solar cells. The hybrid conductive films have been prepared on glass and polyethylene terephthalate (PET) substrates using conventional photolithography process and transfer process of graphene. The optical and electrical properties of prepared conductive films show transmittance of 87% at 550nm and sheet resistance of $28{\Omega}/square$. The electromechanical properties were also investigated in detail to confirm the flexibility of the hybrid films. OSCs have been fabricated on the hybrid conductive films based on graphene and silver grid on glass substrate. The power conversion efficiency of 2.38%, a fill factor of 51%, an open circuit voltage of 0.58V and a short circuit current of $8.05mA/cm^2$ were obtained from the device on glass substrate. The PCE was enhanced 11% compared with OSCs on the MLG films without silver grid.