• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.658-658
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• 2013

Graphene is an attractive material for various device applications due to great electrical properties and chemical properties. However, lack of band gap is significant hurdle of graphene for future electrical device applications. In the past few years, several methods have been attempted to open and tune a band gap of graphene. For example, researchers try to fabricate graphene nanoribbon (GNR) using various templates or unzip the carbon nanotubes itself. However, these methods generate small driving currents or transconductances because of the large amount of scattering source at edge of GNRs. At 2009, Bai et al. introduced graphene nanomesh (GNM) structures which can open the band gap of large area graphene at room temperature with high current. However, this method is complex and only small area is possible. For practical applications, it needs more simple and large scale process. Herein, we introduce a photosensitive graphene device fabrication using CdSe QD coated nano-porous graphene (NPG). In our experiment, NPG was fabricated by thin film anodic aluminum oxide (AAO) film as an etching mask. First of all, we transfer the AAO on the graphene. And then, we etch the graphene using O2 reactive ion etching (RIE). Finally, we fabricate graphene device thorough photolithography process. We can control the length of NPG neckwidth from AAO pore widening time and RIE etching time. And we can increase size of NPG as large as 2 $cm^2$. Thin CdSe QD layer was deposited by spin coatingprocess. We carried out NPG structure by using field emission scanning electron microscopy (FE-SEM). And device measurements were done by Keithley 4200 SCS with 532 nm laser beam (5 mW) irradiation.

• Journal of Sensor Science and Technology
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• v.17 no.5
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• pp.369-374
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• 2008

A novel fiber optic surface plasmon resonance (SPR) sensor using cyclic olefin copolymer (COC) prism with the spectral modulation is presented. The SPR sensor chip is fabricated using the SU-8 photolithography, Ni-electroplating and COC injection molding process. The sidewall of the COC prism is partially deposited with Au/Cr (45/2.nm thickness) by e-beam evaporator, and the thermal bonding process is conducted for micro fluidic channels and optical fibers alignment. The SPR spectrum for a phosphate buffered saline (0.1.M PBS, pH.7.2) solution shows a distinctive dip at 1300.nm wavelength, which shifts toward longer wavelength with respect to the bovine serum albumin (BSA)concentrations. The sensitivity of the wavelength shift is $1.16\;nm{\cdot}{\mu}g^{-1}{\cdot}{\mu}l^{-1}$. From the wavelength of SPR dips, the refractive indices (RI) of the BSA solutions can be theoretically calculated using Kretchmann configuration, and the change rate of the RI was found to be $2.3{\times}10^{-5}RI{\cdot}{\mu}g^{-1}{\cdot}l^{-1}$. The realized fiber optic SPR sensor with a COC prism has clearly shown the feasibility of a new disposable, low cost and miniaturized SPR biosensor for biochemical molecular analyses.

• Journal of the Korean Society of Urban Environment
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• v.18 no.4
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• pp.503-509
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• 2018

In this study, a Proton-Transfer Reaction-Time-of-Flight Mass spectrometer (PTR-TOF-MS) was used for the continuous monitoring of Volatile Organic Compounds (VOCs) emitted from semiconductor workplace such as photolithography (PHOTO), flat panel display (FPD), organic light emitting diode (OLED), etching (WET) process. The averaged VOCs mixing ratio in the such workplace, PHOTO was 6.5 ppm, FPH was 6.4 ppm, WET was 2.0 ppm and OLED was 1.3 ppm, respectively. The abundance of VOCs in the workplace were methyl ethyl ketone (MEK) with 2.8 ppm (69%) and acetaldehyde with 0.5 ppm (13.2%). Depending on the semiconductor process characteristics, various VOCs have been observed in the workplace. The VOCs mixing ratio are lower than the workplace regulation standard (TWA), it is necessary to continuously monitor and effectively manage these VOCs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.1
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• pp.17-21
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• 2011

Copper (Cu) had been attractive material due to its superior properties comparing to other metals such as aluminum or tungsten and considered as the best metal which can replace them as an interconnect metal in integrated circuits. CMP (Chemical Mechanical Polishing) technology enabled the production of excellent local and global planarization of microelectronic materials, which allow high resolution of photolithography process. Cu CMP is a complex removal process performed by chemical reaction and mechanical abrasion, which can make defects of its own such as a scratch, particle and dishing. The abrasive particles remain on the Cu surface, and become contaminations to make device yield and performance deteriorate. To remove the particle, buffing cleaning method used in post-CMP cleaning and buffing is the one of the most effective physical cleaning process. AE(Acoustic Emission) sensor was used to detect dynamic friction during the buffing process. When polishing is started, the sensor starts to be loaded and produces an electrical charge that is directly proportional to the applied force. Cleaning efficiency of Cu surface were measured by FE-SEM and AFM during the buffing process. The experimental result showed that particles removed with buffing process, it is possible to detect the particle removal efficiency through obtained signal by the AE sensor.

• Journal of the Korean Vacuum Society
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• v.21 no.4
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• pp.199-204
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• 2012

$SF_6$ gas is widely used for dry etching process of semiconductor and display fabrication process. But $SF_6$ gas is considered for typical greenhouse gas for global warming. So it is necessary to research relating to $SF_6$ alternatives reducing greenhouse effect in semiconductor and display. $C_3F_6$ gas is one of the promising candidates for it. We studied about etch characteristics by performing Reactive Ion Etching process of dry etching and reduced gas element exhausted on etching process using absorbent Zeolite 5A. $Si_3N_4$ thin film was deposited to 500 nm with Plasma Enhanced Chemical Vapor Deposition and we performed Reactive Ion Etching process after patterning through photolithography process. It was observed that the etch rate and the etched surface of $Si_3N_4$ thin film with Scanning Electron Microscope pictures. And we measured and compared the exhausted gas before and after the absorbent using Gas Chromatograph-Mass Spectrophotometry.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.454-454
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• 2014

Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.7-11
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• 2011

In this paper, we proposed a simple and high-yield printing process for source and drain electrodes of organic thin film transistor (OTFT). The surface energy of PVP (poly 4-vinylphenol) gate dielectric was decreased from 56 $mJ/m^2$ to 45 $mJ/m^2$ by adding fluoride of 3000ppm into it. Meanwhile the surface energy of source and drain (S/D) electrodes area on the PVP was increased to 87 $mJ/m^2$ by treating the areas, which was patterned by photolithography, with oxygen plasma, maximizing the surface energy difference from the other areas. A conductive polymer, G-PEDOT:PSS, was deposited on the S/D electrode areas by brushing painting process. With such a simple process we could obtain a high yield of above 90 % in $16{\times}16$ arrays of OTFTs. The performance of OTFTs with the fluoride-added PVP was similar to that of OTFTs with the ordinary PVP without fluoride, generating the mobility of 0.1 $cm^2/V.sec$, which was sufficient enough to drive electrophoretic display (EPD) sheet. The EPD panel employing the OTFT-backpane successfully demonstrated to display some patterns on it.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.1
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• pp.37-44
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• 2015

In this paper, we have investigated a selective assembly method of single-walled carbon nanotubes (SWCNTs) on a silicon substrate using only photolithographic process and then proposed a fabrication method of field effect transistors (FETs) using SWCNT-based patterns. The aminopropylethoxysilane (APTES) patterns, which are formed for positively charged surface molecular patterns, are utilized to assemble and align millions of SWCNTs and we can more effectively assemble on a silicon (Si) surface using this method than assembly processes using only the 1-octadecyltrichlorosilane (OTS). We investigated a selective assembly method of SWCNTs on a Si surface using surface-programmed APTES and OTS patterns and then a fabrication method of FETs. photoresist(PR) patterns were made using photolithographic process on the silicon dioxide (SiO2) grown Si substrate and the substrate was placed in the OTS solution (1:500 v/v in anhydrous hexane) to cover the bare SiO2 regions. After removing the PR, the substrate was placed in APTES solution to backfill the remaining SiO2 area. This surface-programmed substrate was placed into a SWCNT solution dispersed in dichlorobenzene. SWCNTs were attracted toward the positively charged molecular regions, and aligned along the APTES patterns. On the contrary, SWCNT were not assembled on the OTS patterns. In this process, positively charged surface molecular patterns are utilized to direct the assembly of negatively charged SWCNT on SiO2. As a result, the selectively assembled SWCNT channels can be obtained between two electrodes(source and drain electrodes). Finally, we can successfully fabricate SWCNT-based multi-channel FETs by using our self-assembled monolayer method.

• Clean Technology
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• v.29 no.4
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• pp.255-261
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• 2023

Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.411-411
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• 2012

Over the recent years, surface enhanced Raman spectroscopy (SERS) has dramatically grown as a label-free detecting technique with the high level of selectivity and sensitivity. Conventional SERS-active nanostructured layers have been deposited or patterned on rigid substrates such as silicon wafers and glass slides. Such devices fabricated on a flexible platform may offer additional functionalities and potential applications. For example, flexible SERS-active substrates can be integrated into microfluidic diagnostic devices with round-shaped micro-channel, which has large surface area compared to the area of flat SERS-active substrates so that we may anticipate high sensitivity in a conformable device form. We demonstrate fabrication of flexible SERS-active nanostructured substrates based on soft-lithography for simple, low-cost processing. The SERS-active nanostructured substrates are fabricated using conventional Si fabrication process and inkjet printing methods. A Si mold is patterned by photolithography with an average height of 700 nm and an average pitch of 200 nm. Polydimethylsiloxane (PDMS), a mixture of Sylgard 184 elastomer and curing agnet (wt/wt = 10:1), is poured onto the mold that is coated with trichlorosilane for separating the PDMS easily from the mold. Then, the nano-pattern is transferred to the thin PDMS substrates. The soft lithographic methods enable the SERS-active nanostructured substrates to be repeatedly replicated. Silver layer is physically deposited on the PDMS. Then, gold nanoparticle (AuNP) inks are applied on the nanostructured PDMS using inkjet printer (Dimatix DMP 2831) to deposit AuNPs on the substrates. The characteristics of SERS-active substrates are measured; topology is provided by atomic force microscope (AFM, Park Systems XE-100) and Raman spectra are collected by Raman spectroscopy (Horiba LabRAM ARAMIS Spectrometer). We anticipate that the results may open up various possibilities of applying flexible platform to highly sensitive Raman detection.