• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1297-1298
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• 2006

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have been attracted recently attention due to their highdevice performance expected from theoretical simulations among nanowire-based FETs with other gate geometries. OSG FETs with the channels of ZnO nanowires were successfully fabricated in this study with photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels of ZnO nanowires with diameters of about 60 nm are coated surroundingly by $Al_{2}O_{3}$ as gate dielectrics with atomic layer deposition. About 80 % of the surfaces of the nanowires coated with $Al_{2}O_{3}$ is covered with gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 98.9 $cm^{2}/Vs$, a peak transconductance of 0.4 ${\mu}S$, and an Ion/Ioff ratio of $10^6$ the value of the Ion/Ioff ratio obtained from this OSG FET is the highest among nanowire-based FETs, to our knowledge. Its mobility, peak transconductance, and Ion/Ioff ratio arc remarkably enhanced by 11.5, 32, and $10^6$ times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.

• 한국재료학회지
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• 제29권7호
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• pp.456-462
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• 2019

ZnO thin-films are grown on a p-Si(111) substrate by RF sputtering. The effects of growth temperature and $O_2$ mixture ratio on the ZnO films are investigated by scanning electron microscopy (SEM), X-ray diffraction (XRD), and room-temperature photoluminescence (PL) measurements. All the grown ZnO thin films show a strong preferred orientation along the c-axis, with an intense ultraviolet emission centered at 377 nm. However, when $O_2$ is mixed with the sputtering gas, the half width at half maximum (FWHM) of the XRD peak increases and the deep-level defect-related emission PL band becomes pronounced. In addition, an n-ZnO/p-Si heterojunction diode is fabricated by photolithographic processes and characterized using its current-voltage (I-V) characteristic curve and photoresponsivity. The fabricated n-ZnO/p-Si heterojunction diode exhibits typical rectifying I-V characteristics, with turn-on voltage of about 1.1 V and ideality factor of 1.7. The ratio of current density at ${\pm}3V$ of the reverse and forward bias voltage is about $5.8{\times}10^3$, which demonstrates the switching performance of the fabricated diode. The photoresponse of the diode under illumination of chopped with 40 Hz white light source shows fast response time and recovery time of 0.5 msec and 0.4 msec, respectively.

• 공업화학
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• 제7권2호
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• pp.379-386
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• 1996

광 이량화 특성을 나타내는 1-methyl-4-[2-(4-diethylacetylphenyl)ethenyl] pridinium methosulfate(SbQ-A염)를 dimethyl sulfate, terephthalaldehyde mono-(diethyl acetal) 및 4-picoline을 이용하여 합성하였다. 합성된 SbQ-A염을 PVA와 반응시켜 동일(MW=77,000-79,000g/mol) 분자량을 가진 PVA내 SbQ의 함량이 다른 PVA-SbQ-H 시료 및 SbQ의 함량은 약 1.3mol%로 같으나 PVA의 분자량이 다른 PVA-SbQ-L들을 합성하였다. Gray scale(GS)법을 이용하여 측정된 PVA-SbQ 수용성 감광성 고분자의 상대감도는 PVA내 SbQ의 함량이 증가함에 따라 증가하였으며, PVA의 분자량이 낮아질수록 감소하였다. PVA-SbQ-H의 경우 SbQ 함량이 2.63mol%인 시료는 PVA에 ammonium dichromate가 혼합된 기존시료보다 90배 증가된 감도를 나타내었다. PVA-SbQ를 사용하여 형광체 슬러리를 제조하고 사진식각공정을 거쳐 형광체의 미세패턴을 형성하였다. 형광체 슬러리 제조시 양이온 계면활성제인 cetyltrimethyl ammonium chloride를 첨가제로 사용하면 형광면의 해상도가 증가됨을 알았다.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.1-6
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• 2007

본 연구에서는 모양으로 유도된 자기 이방성을 가진 $Ni_{80}Fe_{20}/SiO_2$ laminates 다층막의 자기적 성질을 조사 하였다. 다층막은 rf 다이오드 스퍼터링 시스템을 이용하여 개개의 $Ni_{80}Fe_{20} 와 $SiO_2$ (at%) 합금 타겟들로부터 Si 또는 upilex 기판에 적층하였다. 여러 가지 개수(N)의 이중층으로 구성된 $Ni_{80}Fe_{20}/SiO_2$ laminates 가 적층되었다. 사진식각기술을 사용하여 타원형 어레이 패턴을 가진 $Ni_{80}Fe_{20}/SiO_2$ laminates 가 제작 되었다. 자기적 성질은 B-H 히스테리시스 그래프와 고주파 permeameter를 사용하여 상온에서 측정 되었다. 다층막에서 도메인 reversal 시 발견된 몇 개의 스텝들은 자성체 박막 사이에 존재하는 coupling 때문으로 사료된다. 내재하는 intrinsic 일축 자기 이방성 field는 N이 증가하면 증가한다. 전체 자기 이방성 field의 실험값은 계산된 값과 잘 일치 하였다. 본 연구에서는 소형의 타원형 어레이를 가진 다층막의 laminate 구조체를 이용하여 더 큰 일축 자기 이방성을 유도하고 그 결과 laminate의 동작 주파수를 극대화시키고자 하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.77-77
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• 2000

Titanium oxide (TiO2) thin films have valuable properties such as a high refractive index, excellent transmittance in the visible and near-IR frequency, and high chemical stability. Therefore it is extensively used in anti-reflection coating, sensor, and photocatalysis as electrical and optical applications. Specially, TiO2 have a high dielectric constant of 180 along the c axis and 90 along the a axis, so it is highlighted in fabricating dielectric capacitors in micro electronic devices. A variety of methods have been used to produce patterned self-assembled monolayers (SAMs), including microcontact printing ($\mu$CP), UV-photolithotgraphy, e-beam lithography, scanned-probe based micro-machining, and atom-lithography. Above all, thin film fabrication on $\mu$CP modified surface is a potentially low-cost, high-throughput method, because it does not require expensive photolithographic equipment, and it produce micrometer scale patterns in thin film materials. The patterned SAMs were used as thin resists, to transfer patterns onto thin films either by chemical etching or by selective deposition. In this study, we deposited TiO2 thin films on Si (1000 substrateds using titanium (IV) isopropoxide ([Ti(O(C3H7)4)] ; TIP as a single molecular precursor at deposition temperature in the range of 300-$700^{\circ}C$ without any carrier and bubbler gas. Crack-free, highly oriented TiO2 polycrystalline thin films with anatase phase and stoichimetric ratio of Ti and O were successfully deposited on Si(100) at temperature as low as 50$0^{\circ}C$. XRD and TED data showed that below 50$0^{\circ}C$, the TiO2 thin films were dominantly grown on Si(100) surfaces in the [211] direction, whereas with increasing the deposition temperature to $700^{\circ}C$, the main films growth direction was changed to be [200]. Two distinct growth behaviors were observed from the Arhenius plots. In addition to deposition of THe TiO2 thin films on Si(100) substrates, patterning of TiO2 thin films was also performed at grown temperature in the range of 300-50$0^{\circ}C$ by MOCVD onto the Si(100) substrates of which surface was modified by organic thin film template. The organic thin film of SAm is obtained by the $\mu$CP method. Alpha-step profile and optical microscope images showed that the boundaries between SAMs areas and selectively deposited TiO2 thin film areas are very definite and sharp. Capacitance - Voltage measurements made on TiO2 films gave a dielectric constant of 29, suggesting a possibility of electronic material applications.

• 비파괴검사학회지
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• 제36권1호
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• pp.18-26
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• 2016

반도체 산업은 우리나라 주력산업중 하나로 매년 꾸준한 성장세를 보이며 지속적인 성장을 하고 있다. 이러한 반도체 산업에서의 중요한 기술은 소자의 고 집적화이다. 이는 면적당 메모리 용량을 증가시키는 것으로 핵심역할을 하는 것이 바로 포토리소그래피 기술이다. 포토리소그래피란 마스크의 표면에 빛을 쬐어 생기는 그림자를 웨이퍼 상에 인쇄하는 기술이며 반도체 제조공정에서의 가장 중요한 공정이다. 이러한 공정을 통해 나온 패터닝을 분석 시에 폭과 단차의 균일성을 측정한다. 이에 따라 본 논문은 포토리소그래피 공정이 적용된 시험편 패터닝에 폭과 판 사이와의 단차를 투과형 디지털 홀로그래피를 구성하여 측정하고자 한다. 투과형 디지털 홀로그래피 간섭계를 구성하고 시험편에 임의의 9포인트를 설정하여 각 포인트를 측정하고 상용장비인 SEM (scanning electron microscopy)과 alpha step으로 측정한 결과와 비교하고자 한다. 투과형 디지털 홀로그래피는 측정시간이 타 기법에 비에 짧다는 장점과 배율렌즈를 사용하기 때문에 저 배율에서 고 배율로 변경하여 측정할 수 있는 장점을 가지고 있다. 실험 결과로부터 투과형 디지털 홀로그래피가 포토 리소그래피가 적용된 패터닝 측정에 유용한 기술임을 확인할 수 있었다.