• Title/Summary/Keyword: Photo Transistor

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Implementation of Real-time Measurement Hardware for Activity of Water Flea and Remote Monitoring System using CCD Camera (CCD 카메라를 사용한 물벼룩의 실시간 활동량 측정 하드웨어와 원격 모니터링 시스템 구현)

  • Park, Se-Huyn;Park, Se-Hoon;Kim, Eung-Soo
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.5
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    • pp.30-37
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    • 2007
  • Hardware for monitoring the water quality is developed using water fleas. Water flea is a frequently used biological sensor for monitoring the water quality. Water fleas quickly respond to the incoming toxic water by changing their activity when they are exposed. By measuring the activity of water fleas, the incoming toxic water is instantly detected in real time. So far the measurement of activity of water fleas has been done with a system equipped with a light source of LED and a light detector of photo transistor. Water flea itself is, however, sensitive to light resulting in incorrect response and the system has two inconvenient separate parts of the light source and the detector. This paper suggests a system using a CCD camera instead of a light source and a detector. The suggested system processes the image data from the CCD camera in real time without any delay. The developed system becomes a part of the remote water monitoring embedded system.

UV Responsive Characteristics of n-Channel Schottky Barrier MOSFET with ITO as Source/Drain Contacts

  • Kim, Tae-Hyeon;Lee, Chang-Ju;Kim, Dong-Seok;Sung, Sang-Yun;Heo, Young-Woo;Lee, Jung-Hee;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.20 no.3
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    • pp.156-161
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    • 2011
  • We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.

그래핀 전계효과 트랜지스터의 광응답 특성

  • Lee, Dae-Yeong;Min, Mi-Suk;Ra, Chang-Ho;Lee, Hyo-Yeong;Yu, Won-Jong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.193-194
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    • 2012
  • 그래핀(graphene)은 탄소원자가 육각형 벌집 모양 배열의 격자구조를 가지는 원자 한층 두께의 이차원 물질이다. 그래핀은 전도띠(conduction band)와 가전자띠(valence band)가 한 점에서 만나고 에너지와 역격자의 k 벡터가 선형적으로 비례하는 에너지 구조를 가진다. 이로 인해 그래핀은 매우 빠른 전하 이동도를 가지며 원자 한 층의 두께임에도 불구하고 약 2.3%의 빛을 흡수할 수 있으며 자외선 영역부터 적외선 영역까지의 넓은 파장대의 빛을 흡수 할 수 있다. 이와 같은 그래핀의 우월한 성질을 이용하면 광 응답에 고속으로 반응하고 높은 주파수의 광통신에서도 작동 할 수 있는 그래핀 광소자를 제작할 수 있게 된다. 하지만 미래의 고속 그래핀 광소자를 실현하기에 앞서 그래핀의 광응답에 대한 정확한 이해가 필요하다. 그리하여 본 연구에서는 그래핀 광소자를 제작하고 광소자의 광응답 전기적 성질을 분석하여 그래핀의 광응답 특성을 얻어내고자 실험을 진행하였다. 그래핀을 채널 물질로 하고 소스, 드레인, 후면 게이트를 가지는 일반적인 그래핀 전계효과 트랜지스터(field-effect transistor)를 제작하고 채널에 빛을 비추고 비추지 않은 상태에서의 전기적 성질을 측정하고 그 때 얻어진 그래프의 광응답의 원인을 조사하였다. 이 때 얻어지는 $I_D-V_G$ 그래프가 광 조사 시 왼쪽으로 이동하게 되는데 이의 원인을 각 게이트 전압 구간별로 $I_D$-t 그래프를 획득하여 분석하였다. 또한 광원에 펄스를 인가하여 펄스 형태의 광원을 그래핀 전계효과 트랜지스터에 조사시키고 이에 따른 전기적 성질 변화를 관찰하였다 이 때 다양한 게이트 전압이 인가된 상태에서 레이저 펄스 광원에 의한 광전류를 검출하였으며 이를 분석하였다.

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Fabrication of Hydrogel and Gas Permeable Membranes for FET Type Dissolved $CO_{2}$ Sensor by Photolithographic Method (사진식각법을 이용한 FET형 용존 $CO_{2}$ 센서의 수화젤막 및 가스 투과막 제작)

  • Park, Lee-Soon;Kim, Sang-Tae;Koh, Kwang-Nak
    • Journal of Sensor Science and Technology
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    • v.6 no.3
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    • pp.207-213
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    • 1997
  • A field effect transistor(FET) type dissolved carbon dioxide($pCO_{2}$) sensor with a double layer structure of hydrogel membrane and $CO_{2}$ gas permeable membrane was fabricated by utilizing a $H^{+}$ ion selective field effect transistor(pH-ISFET) with Ag/AgCl reference electrode as a base chip. Formation of hydrogel membrane with photo-crosslinkable PVA-SbQ or PVP-PVAc/photosensitizer system was not suitable with the photolithographic process. Furthermore, hydrogel membrane on pH-ISFET base chip could be fabricated by photolithographic method with the aid of N,N,N',N'-tetramethyl othylenediarnine(TED) as $O_{2}$ quencher without using polyester film as a $O_{2}$ blanket during UV irradiation process. Photosensitive urethane acrylate type oligomer was used as gas permeable membrane on top of hydrogel layer. The FET type $pCO_{2}$ sensor fabricated by photolithographic method showed good linearity (linear calibration curve) in the range of $10^{-3}{\sim}10^{0}\;mol/{\ell}$ of dissolved $CO_{2}$ in aqueous solution with high sensitivity.

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The study of ${\mu}c-Si/CaF_2$/glass properties for thin film transistor application (박막트랜지스터 응용을 위한 ${\mu}c-Si/CaF_2$/glass 구조특성연구)

  • Kim, Do-Young;Ahn, Byeung-Jae;Lim, Dong-Gun;Yi, Jun-Sin
    • Proceedings of the KIEE Conference
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    • 1999.07d
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    • pp.1514-1516
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    • 1999
  • This paper covers our efforts to improve the low carrier mobility and light instability of hydrogenated amorphous silicon (a-Si:H) films with microcrystalline silicon $({\mu}c-Si)$ films. We successfully prepared ${\mu}c-Si$ films on $CaF_2$/glass substrate by decomposition of $SiH_4$ in RPCVD system. The $CaF_2$ films on glass served as a seed layer for ${\mu}c-Si$ film growth. The XRD analysis on $CaF_2$/glass illustrated a (111) preferred $CaF_2$ grains with the lattice mismatch less than 5 % of Si. We achieved ${\mu}c-Si$ films with a crystalline volume fraction of 61 %, (111) and (220) crystal orientations. grain size of $706\AA$, activation energy of 0.49 eV, and Photo/dark conductivity ratio of 124. By using a $CaF_2$/glass structure. we were able to achieve an improved ${\mu}c-Si$ films at a low substrate temperature of $300^{\circ}C$.

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Poly-Si Thin Film Transistor with poly-Si/a-Si Double Active Layer Fabricated by Employing Native Oxide and Excimer Laser Annealing (자연 산화막과 엑시머 레이저를 이용한 Poly-Si/a-Si 이중 박막 다결정 실리콘 박막 트랜지스터)

  • Park, Gi-Chan;Park, Jin-U;Jeong, Sang-Hun;Han, Min-Gu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.1
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    • pp.24-29
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    • 2000
  • We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

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2.22-inch qVGA ${\alpha}$-Si TFT-LCD Using a 2.5 um Fine-Patterning Technology by Wet Etch Process

  • Lee, J.B.;Park, S.;Heo, S.K.;You, C.K.;Min, H.K.;Kim, C.W.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.1649-1652
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    • 2006
  • 2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (${\alpha}$- Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated because the 2.5 um fine pattern formation technique is combined with high thermal photo-resist (PR) development. In addition, a novel concept of unique ${\alpha}$-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um finepatterning is a considerably significant technology to obtain higher aperture ratio for higher resolution ${\alpha}$-Si TFT-LCD panel realization.

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Performance of Zn-based oxide thin film transistors with buried layers grown by atomic layer deposition

  • An, Cheol-Hyeon;Lee, Sang-Ryeol;Jo, Hyeong-Gyun
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2012.05a
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    • pp.77.1-77.1
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    • 2012
  • Zn 기반 산화물 반도체는 기존의 비정질 Si에 비해 저온공정에도 불구하고 높은 이동도, 투명하다는 장점으로 인해 차세대 디스플레이용 백플레인 소자로 주목받고 있다. 산화물 트랜지스터는 우수한 소자특성을 보여주고 있지만, 온도, 빛, 그리고 게이트 바이어스 스트레스에 의한 문턱전압의 불안정성이 문제의 문제를 해결해야한다. 산화물 반도체의 문턱전압의 불안정성은 유전체와 채널층의 계면 혹은 채널에서의 charge trap, photo-generated carrier, ads-/desorption of molecular 등의 원인으로 보고되고 있어, 고신뢰성의 산화물 채널층을 성장하기 위한 노력이 이루어지고 있다. 최근, 산화물 트랜지스터의 다양한 조건에서의 문턱전압의 불안정성을 해결하기 위해 산화물의 주된 결함으로 일컬어지고 있는 산소결핍을 억제하기 위해 성장공정의 제어 그리고, 산소와의 높은 binding energy를 같은 Al, Hf, Si 등과 같은 원소를 첨가하여 향상된 소자의 특성이 보고되고 있지만, 줄어든 산소공공으로 인해 이동도가 저하되는 문제점이 야기되고 있다. 이러한 문제점을 해결하기 위해, 최근에는 Buried layer의 삽입 혹은 bi-channel 등과 같은 방안들이 제안되고 있다. 본 연구는 atomic layer deposition을 이용하여 AZO bureid layer가 적용된 ZnO 트랜지스터의 특성과 안정성에 대한 연구를 하였다. 다결정 ZnO 채널은 유전체와의 계면에 많은 interface trap density로 인해 positive gate bias stress에 의한 문턱전압의 불안정성을 보였지만, AZO층이 적용된 ZnO 트랜지스터는 줄어든 interface trap density로 인해 향산된 stability를 보였다.

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A Study on the Electrical Characteristics of Pentacene Organic Thin Film Transistor using Organic Gate Insulator (유기물 게이트 절연체를 사용한 pentacene 유기 박막 트랜지스터의 전기적 특성에 관한 연구)

  • Kim, Yun-Myoung;Kim, Ok-Byoung;Kim, Jung-Soo;Kim, Young-Kwan;Zyung, Tae-Hyung
    • Proceedings of the KIEE Conference
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    • 2000.11c
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    • pp.446-448
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    • 2000
  • Organic semiconductors based on vacuum-deposited films of fused-ring polycyclic aromatic hydrocarbon have great potential to be utilized as an active layer for electronic and optoelectronic devices. In this study, pentacene thin films and electrode materials were deposited by Organic Molecular Beam Deposition (OMBD) and vacuum evaporation respectively. For the gate dielectric layer, OPTMER PC403 photo acryl (JSR Coporation.) was spin-coated and cured at $220^{\circ}C$. Electrical characteristics of the devices were investigated, where the channel length and width was $50{\mu}m$ and 5 mm. It was found that field effect mobility was $0.039\;cm^2V^{-1}s^{-1}$, threshold voltage was -7 V, and on/off current ratio was $10^6$.

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Channel Protection Layer Effect on the Performance of Oxide TFTs

  • KoPark, Sang-Hee;Cho, Doo-Hee;Hwang, Chi-Sun;Yang, Shin-Hyuk;Ryu, Min-Ki;Byun, Chun-Won;Yoon, Sung-Min;Cheong, Woo-Seok;Cho, Kyoung-Ik;Jeon, Jae-Hong
    • ETRI Journal
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    • v.31 no.6
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    • pp.653-659
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    • 2009
  • We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.