• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.635-645
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• 2016

In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

• International Journal of Control, Automation, and Systems
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• v.3 no.spc2
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• pp.346-354
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• 2005

This paper presents a new approach to Thyristor Controlled Phase Shifter (TCPS) control. In this paper we have proposed a nonlinear coordinated generator excitation and TCPS controller to enhance the transient stability of a power system. The proposed controller is able to control three main parameters affecting a.c. power transmission: namely excitation voltage, phase angle and reactance in a coordinated manner. The TCPS is located at the midpoint of the transmission line. A nonlinear feedback control law is proposed to linearize and decouple the power system. The design of the proposed controller is based on the local measurements only. Simulation results have been shown to demonstrate the effectiveness of the proposed controller for the enhancement of transient stability of the power system under a large sudden fault.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.364-366
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• 2008

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.319-319
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• 2004

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.141-144
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• 2003

In this paper, a PWM Cuk AC-AC converter for WCF applications such as AC line conditioner, phase shifter is presented. The PWM Cuk AC-AC converter is modelled by using complex circuit DQ transformation whereby the characteristics equations such as voltage gain and the interested voltage and current is analytically obtained. Finally, the PSIM simulation show the validity of the modelling and analysis.

• Proceedings of the KIEE Conference
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• summer
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• pp.1158-1160
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• 2004

In this paper, a PWM SEPIC AC-AC converter for VVCF applications such as AC line conditioner, phase shifter is presented. The PWM SEPIC AC-AC converter is modelled by using complex circuit DQ transformation whereby the characteristics equations such as voltage gain and input power factor is analytically obtained. Finally, the PSIM simulation shows the validity of the modelling and analysis.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.34 no.4
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• pp.265-272
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• 2017

Velocity ripple in manufacturing processes reduces productivity and limits the precision of the product. In practice, the frequency and phase of velocity ripples always change minutely, which makes it impossible to compensate for the ripple by simply inserting an opposite feed-forward signal in the system. In this study, an active-phase compensation algorithm was developed to enable the velocity-ripple controller to track the phase change of the ripples in real time. The proposed controller can compensate for the velocity ripple whatever its cause, including disturbance by the torque ripple. The algorithm consists of three functional modules: the velocity-ripple extractor, the synchronized integrator, and the phase shifter. Experimental results showed that the proposed controller clearly reduces velocity ripples with phase variation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.2
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• pp.308-315
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• 2001

In this paper, a new power amplifier is proposed for reduction of amplified RX band noise signals as well as intermodulation distortion signals using feedforward technique. This power amplifier is implemented for IMT-2000 basestation TX frequency band. Both TX band intermodulation distortion signals and RX band noise signals are reduced by controlling variable attenuator, phase shifter and error amplifier. The proposed power amplifier, which contains two loops-intermodulation distortion signals cancellation loop and RX band noise signals cancellation loop, can provide duplexer with low TX path insertion loss for various wireless communication systems due to choice of loose RX attenuation characteristic. The principle of the proposed amplifier is described graphically based on the conceptual schematic diagram. A two-tone test for power amplifier is done at 2.14GHz with frequency spacing of 5MHz, and RX band rejection test is done over RX full band of 60MHz with 1.95GHz center frequency. Experimental results represent that the cancellation performance of intermodulation distortion signals and RX band noise signals are more than 3 1dB and 21dB, respectively.