• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.109-116
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• 2004

In a satellite time management system, the GPS-based clock synchronization technique[1] has the merits of precision time management by knowing the time difference or the error between the OBT(On Board Time) of the internal processors and GPS time every second. It can be realized employing the DPLL(Digital Phase Loop Lock) and FEP(Front End Processor) circuitry for the clock synchronization[2]. In this paper, a refined DPLL & FEP scheme is proposed to provide the precision, stability and robustness of the operation, which is to compensate the errors and noise of the GPS signal, and also to cope with the case when the GPS signal is lost due to several reasons. The simulation and HIL (Hardware In the Loop) test results using the FM(Flight Model) in the course of KOMPSAT-2(Korea Multi Purpose Satellite-2) design and development are illustrated to demonstrate the salient features of this methodology.

• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1840-1842
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• 1998

Gyroscope is a very important core sensor, as a rotation sensor in inertial space, in inertial guidance and navigation system on aeronautics, plane, vessel and so on for civilian and millitary applications. Mechnical gyroscopes, adopting a principle of spinning a top, have been used in many application system. These mechnical gyroscopes need high power consumption, long warming time and complicated peripheral devices. But fiber-optic gyroscopes, based on the Sagnac effect, have novel advantages as small volume. simple scheme, low power consumption and high reliability. So we have developed a Intermediate grade All-fiber Optic Gyroscope, which has open-loop and minimum reciprocal configuration scheme. We have designed feedback circuits for stability of amplitude and phase using four lock-in amplifier(LIA) circuits and also used for noise limitation. This paper describes the scheme of optical part and electronic part and also test results of this all-fiber optic gyroscope. The performance have been achieved as long-term bias drift of $9.54^{\circ}/h$, random walk of $0.0317^{\circ}/\sqrt{h}$ and dynamic range of ${\pm}150\;deg/s$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.845-848
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• 2005

This paper describes a 4.224GHz CMOS charge pump PLL for Mode 1 MB-OFDM UWB hopping carrier generation. It includes a qudrature VCO of which the frequency range is from 3.98GHz to 4.47GHz(@ 0.4 to 1.5 V), a divider, a PFD, a loop filter, a charge pump, and a lock detector. Designed in a 0.18um CMOS technology, the PLL draws 6.6mA from a 1.8V supply. The phase noise of the designed VCO is -133dBc/Hz@3MHz.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.56 no.2
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• pp.90-98
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• 2007

More and All-Electric Aircraft (AEA) carry many loads with varied functions. In particular, there may be large pulsed loads with short duty ratio, which can affect the normal operation of other loads. In this paper, a bi-directional converter with inductive storage is used as a voltage bus conditioner (VBC) to mitigate voltage transients on the bus. In addition, the constant frequency hysteresis control technique for a VBC is presented. A simple and fast prediction of the hysteresis band-width is implemented by the phase-lock loop control, keeping constant switching frequency. This technique offers the excellent dynamic response in load or parameter variation. The control performance is illustrated by simulated results with the SABER package, The proposed hysteresis control results in the shortest and the smallest excursions.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.361-364
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• 1998

주파수 합성기는 주로 PLL을 이용하여 설계하는데, PLL(Phase-lock loop)이란 출력신호 주파수를 항상 일정하게 유지하도록 구성된 주파수 부귀환 회로로써 기본적인 구성은 위상출력기, 저역통과필터, 전압 제어 발진기로 이루어진다. 이런 PLL의 기본적인 구성에 프로그래머블카운터를 VCO의 출력단에 부가하여 구성한 형태가 주파수합성기이다. 이 주파수합성기의 출력을 프로그래머블 디바이더에 입력하기 전에 주파수를 낮출 필요가 있는데, 현재 슈퍼헤테로다인 다운 컨버터방식과 프리스케일러방식과 펄스 스웰로 카운터를 사용하는 방식 등의 3가지 방법이 있다. 본 논문에서는 펄스 스웰로 카운터 방식의 주파수 합성기를 MATLAB의 GUI환경과 병행하여 시뮬레이션 과정을 통한 동작특성을 이해하고, 한 화면에서 이루어지는 조작에 의해 모든 주파수 합성기의 요소를 관찰할 수 있도록 모델링하였다. 그리고, 모델링한 주파수합성기와 실제 주파수합성기에서 예상되는 출력과 비교하여 그 결과에 있어서 얼마나 유사한지 살펴보았다.

• Proceedings of the KIEE Conference
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• 2008.11a
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• pp.472-475
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• 2008

A DC distributed power system(DPS) has many loads with varied functions. In particular, there may be large pulsed toads with short duty ratio, which can affect the normal operation of other loads. In this paper, a bi-directional converts with inductive storage is used as a DC bus conditioner to damp voltage transients on the bus. In addition, the constant frequency hysteresis control technique for a DC bus conditioner is presented. A simple and fast prediction of the hysteresis band-width is implemented by the phase-lock loop control, keeping constant switching frequency. This technique offers the excellent dynamic response in load or parameter variation. The control performance is illustrated by simulated results with the SABER package. The proposed hysteresis control results in the shortest and the smallest excursions.

• Journal of Yeungnam Medical Science
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• v.6 no.2
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• pp.63-70
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• 1989

This paper describes to design and to examine the mechanical characteristics of high frequency jet ventilator. The device consists of Phase lock loop(PLL) system, solenoid valve driving control part and Air regulating system. This study is carried out by changing several factors such as endotracheal tube(E.T. tube)diameter, injector cannula diameter, 1%, and frequency(breaths/mim.) having direct effects on the gas exchange as well as parameters of the entrained gas by venturi effects, so as to measure the tidal volume and minute volume. This system characteristics were as follows : 1) Frequency : 6-594bpm 2) Inspiration time : 1-99% 3) Variance of input air pressure : 1-30PSI.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.2
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• pp.80-84
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• 2008

In this paper, we have posed contactless power supply method using the contactless transformer with multiple primary winding. Also, the system uses resonant frequency tracking method for safe power supply at the elevator's car. The proposed system has been verified by the simulation using ICA4 and Maxwell. The contactless power transmission system is designed for 5[kW] rate.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.1
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• pp.25-30
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• 1972

Data Communication by sending pulse train and verifying the lock-in of a phase locked loop in receiving end is studied. The noise rejection property inherent to PLL is analysed. By using about six pulses in a train, data transimission rate of 20k bit/sec. in a telephone cable is achieved, thus permitting high speed data communication and an exellent immunity against noise.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.